Investigations on Surge Current Capability and Failure Mechanism of SiC MOSFETs in Third Quadrant

IF 3.6 2区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE Transactions on Electron Devices Pub Date : 2026-09-01 Epub Date: 2026-07-23 DOI:10.1109/TED.2026.3714364

Zixuan Ye;Xiaochuan Deng;Haohao Dai;Xing Zeng;Hexin Zhu;Xu Li;Xuan Li;Bo Zhang

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Abstract

In this article, the surge current capability and failure mechanism of double trench-gate and planar-gate SiC MOSFETs (DT-MOS and P-MOS) in the third quadrant (including channel turn-on and channel turn-off mode) are investigated. The maximum surge peak of double trench-gate SiC MOSFET (DT-MOS) reaches 38 and 63 A in channel turn-on mode (gate voltage of +15 V) and channel turn-off mode (gate voltage of −5 V), respectively. The surge current capability of DT-MOS in channel turn-on mode has decreased by 41.6% compared with channel turn-off mode. However, the maximum surge peak of planar-gate SiC MOSFET (P-MOS) is found to be similar in channel turn-on mode and turn-off mode (78 and 76 A). A similar failure phenomenon for P-MOS occurs under two different gate–source biases by decapsulation analysis. This is because the excessive temperature in P-MOS under surge current events produces the melting of wire or metal layers and gate–source short. Whereas, DT-MOS exhibits a distinctive difference in failure mechanism after the surge stress at a gate voltage of +15 V. The distinct localized burnout spot has been observed in the transition region of the failed device. Finite element simulation and equivalent circuit analysis indicate that the transition region conducts 14% of the total surge current in the channel turn-on mode, whereas that of the channel turn-off mode is only 5.9%. Due to the limited area of the transition region, the excessive transition current density triggers thermal runaway and localized burnout, degrading the surge current capability of DT-MOS in the channel turn-on mode.

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第三象限SiC mosfet浪涌电流性能及失效机理研究

本文研究了双沟栅和平面栅SiC mosfet （DT-MOS和P-MOS）在第三象限（包括通道导通和关断模式）的浪涌电流能力和失效机理。双沟栅SiC MOSFET （DT-MOS）在通道导通模式（栅极电压为+15 V）和通道关断模式（栅极电压为- 5 V）下的最大浪涌峰值分别达到38和63 A。在通道导通模式下，DT-MOS的浪涌电流能力比通道关断模式下降了41.6%。然而，平面栅极SiC MOSFET （P-MOS）的最大浪涌峰值在通道导通模式和关断模式下（78和76 A）是相似的。通过解封装分析，P-MOS在两种不同的门源偏差下也出现了类似的失效现象。这是因为在浪涌电流作用下，P-MOS中的温度过高会导致导线或金属层熔化和栅极源短路。而在+15 V栅极电压下，DT-MOS在浪涌应力作用下的失效机制存在明显差异。在失效器件的过渡区观察到明显的局部烧蚀点。有限元仿真和等效电路分析表明，在通道导通模式下，过渡区传导的浪涌电流占总浪涌电流的14%，而在通道关断模式下，过渡区传导的浪涌电流仅占5.9%。由于过渡区面积有限，过高的过渡电流密度会引发热失控和局部烧毁，降低了DT-MOS在通道导通模式下的浪涌电流能力。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Transactions on Electron Devices 工程技术-工程：电子与电气

CiteScore

5.80

自引率

16.10%

发文量

937

审稿时长

3.8 months

期刊介绍： IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanoelectronics, optoelectronics, photovoltaics, power ICs and micro-sensors. Tutorial and review papers on these subjects are also published and occasional special issues appear to present a collection of papers which treat particular areas in more depth and breadth.