Back-Gate Effect Mechanism and Mitigation in High-Voltage Thick-Layer SOI pLDMOS Using a Field Plate-Bulk Dual Depletion Structure

Abstract

The impact of the back-gate effect on the breakdown voltage (BV) of high-voltage thick-layer p-channel laterally diffused MOSFET (pLDMOS) is investigated, and the design challenge of achieving low specific on-resistance ( ${R} _{\text {on,sp}}$ ) posed by the back-gate effect is analyzed. A novel pLDMOS featuring a field plate-bulk dual depletion (FP-BD) structure is proposed. By implementing a graded doping profile in the drift region to form a buried N-bulk layer, the structure enables dual depletion between the bulk layer and the surface field plate. This produces a quasi-RESURF electric field distribution, transforming the surface electric field from a single-peak to a double-peak profile. Experimental results show that as the back-gate-to-source voltage sweeps from 0 to −200 V, the BV of the proposed FP-BD pLDMOS decreases by only 12.0%, compared to a 48.2% drop in the conventional device. Furthermore, the structure achieves an extremely low ${R} _{\text {on,sp}}$ of 21.04 m $\Omega {\cdot }\text {cm}^{2}$ at a BV of 283.1 V, representing a 57.8% reduction relative to the RESURF condition. Highly compatible with standard process platforms, this FP-BD structure provides an effective performance-optimization solution for high-voltage thick-layer SOI devices.