Nonvolatile OR Logic Gates Enabled by Single Quad-RRAM Device

Abstract

Implementing energy-efficient in-memory computing with minimized hardware overhead remains a critical challenge. In this study, a monolithically integrated quad-resistive random access memory (RRAM) device is proposed and experimentally verified for area-efficient “OR” logic operations. A vertically stacked TiN/HfO2/Pt/HfO2/TiN structure is adopted to integrate four RRAM cells within a single device footprint. The intermediate common electrode is utilized to effectively decouple the potential distributions of the upper and lower layers, thereby enabling parallel multiport excitation without electrical crosstalk. To elucidate the underlying physics, a 3-D kinetic Monte Carlo (KMC) simulation framework is established to visualize the field-driven stochastic filamentary evolution. Compared with conventional CMOS-based “OR” logic gates, the device count for the proposed device is reduced from 6 to 1, and correspondingly, the footprint can be saved by 83.3%. Furthermore, zero static power consumption is achieved due to the nonvolatility of the HfO2 layer. This single-device logic paradigm demonstrates high potential for high-density 3-D integrated computing systems.