{"title":"Impact of Dislocations on Minority Carrier Lifetime in 300-mm Si Wafers During a High Thermal Budget Process","authors":"Jiuyang Yuan;Bozhou Cai;Yoshiji Miyamura;Wataru Saito;Shin-Ichi NIshizawa","doi":"10.1109/JEDS.2025.3637754","DOIUrl":null,"url":null,"abstract":"A quantitatively analysis of the impact of process-induced dislocations on minority carrier lifetime in 300-mm Si wafer was presented. High thermal budget processes, such as oxidation and impurity diffusion, are essential in Insulated Gate Bipolar Transistor (IGBT) fabrication but can induce dislocations in large-diameter Si wafers. These dislocations may degrade the minority carrier lifetime, directly impairing device performance. Therefore, establishing a quantitative relationship between dislocation density and lifetime is crucial for process control and yield improvement. In this paper, we first demonstrate that dislocation propagation during thermal processes can be effectively suppressed by controlling the magnitude of a parameter “f”, which represents the dislocation propagation rate. Subsequently, wafers with varying dislocation density were fabricated through a series of consecutive thermal cycles. The dislocation density was determined by numerical calculation, while the corresponding minority carrier lifetime was measured using the micro-photoconductivity decay (<inline-formula> <tex-math>$\\mu $ </tex-math></inline-formula>-PCD) method. A quantitative correlation between dislocation density and lifetime was established. These findings contribute to preventing dislocation-induced lifetime degradation during high thermal budget process in power device manufacturing.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"553-560"},"PeriodicalIF":2.9000,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11269314","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Journal of the Electron Devices Society","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/11269314/","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"2025/11/26 0:00:00","PubModel":"Epub","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
A quantitatively analysis of the impact of process-induced dislocations on minority carrier lifetime in 300-mm Si wafer was presented. High thermal budget processes, such as oxidation and impurity diffusion, are essential in Insulated Gate Bipolar Transistor (IGBT) fabrication but can induce dislocations in large-diameter Si wafers. These dislocations may degrade the minority carrier lifetime, directly impairing device performance. Therefore, establishing a quantitative relationship between dislocation density and lifetime is crucial for process control and yield improvement. In this paper, we first demonstrate that dislocation propagation during thermal processes can be effectively suppressed by controlling the magnitude of a parameter “f”, which represents the dislocation propagation rate. Subsequently, wafers with varying dislocation density were fabricated through a series of consecutive thermal cycles. The dislocation density was determined by numerical calculation, while the corresponding minority carrier lifetime was measured using the micro-photoconductivity decay ($\mu $ -PCD) method. A quantitative correlation between dislocation density and lifetime was established. These findings contribute to preventing dislocation-induced lifetime degradation during high thermal budget process in power device manufacturing.
期刊介绍:
The IEEE Journal of the Electron Devices Society (J-EDS) is an open-access, fully electronic scientific journal publishing papers ranging from fundamental to applied research that are scientifically rigorous and relevant to electron devices. The J-EDS publishes original and significant contributions relating to the theory, modelling, design, performance, and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanodevices, optoelectronics, photovoltaics, power IC''s, and micro-sensors. Tutorial and review papers on these subjects are, also, published. And, occasionally special issues with a collection of papers on particular areas in more depth and breadth are, also, published. J-EDS publishes all papers that are judged to be technically valid and original.