Merged-Reference-Compatible Offset-Canceling Discharge-Based Sensing Circuit for STT-MRAM in 28-nm CMOS

Abstract

This article proposes an offset-canceling (OC) discharge-based sensing circuit (OCDC) for spin-transfer-torque magnetic random access memory (STT-MRAM). The proposed circuit simultaneously implements a merged reference line (MRL) architecture and threshold voltage ( $\mathbf {V}_{\mathbf {TH}}$ ) mismatch cancellation, resolving the structural incompatibility between the conventional OC schemes and MRL. A diode-connection-based, self-biasing mechanism further eliminates the need for an external clamp voltage generator, providing robustness against process-voltage-temperature (PVT) variations. A 30 720-bit test chip fabricated in a 28-nm FD-SOI process demonstrates that at $\mathbf {V}_{\mathbf {DD}} =0.8$ V and $\mathbf {t}_{\mathbf {sen}} = 2$ ns, the OCDC reduces the fail bit count (FBC) from 2007 to 0 for Read 0 and from 3957 to 0 for Read 1 compared to the conventional sensing circuit. The robustness of the proposed circuit is further validated through Monte Carlo simulations over a temperature range from −45°C to 90°C and a magnetic tunnel junction (MTJ) resistance variation ranging from 6% to 15%.