Mitigating Process-Induced Wafer Distortion for Enhanced Overlay and Thickness Uniformity

Abstract

Temperature nonuniformity during rapid thermal processing (RTP) induces localized thermal stress and plastic distortion, leading to lithographic overlay errors and yield degradation. In this work, we report a systematic methodology to detect and mitigate process-induced wafer distortion and residual overlay errors without compromising film thickness uniformity. In-plane distortion (IPD) data are used to quantitatively correlate nonuniform residual wafer shape changes with downstream overlay performance with high accuracy. By optimizing the pyrometer T7 offset, residual overlay is reduced to 24.2% and 20.2% of the original values in the X and Y directions, respectively. While conventional tuning typically compromises wafer edge thickness, the incorporation of a side gas injector enables simultaneous improvement in oxide thickness uniformity from 1.33% to 0.18%. This integrated approach demonstrates a practical method for enhancing RTP control and improving overlay performance in advanced semiconductor manufacturing.