Mitigation of Buffer Trap Induced Current Collapse in Quaternary Double Channel Graded-Barrier InAlGaN/GaN HEMTs

IF 2.7 3区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE Transactions on Device and Materials Reliability Pub Date : 2026-06-01 Epub Date: 2026-04-13 DOI:10.1109/TDMR.2026.3683329

Shivansh Awasthi;Vikas Kumar;Ankur Gupta

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引用次数: 0

Abstract

In this work, the current collapse (CC) behavior and reliability improvement of a double-channel graded-barrier high electron mobility transistor (DCGB HEMT) employing an InAlGaN-based quaternary top barrier are investigated using numerical simulations. The proposed DCGB architecture enhances gate electrostatic control and carrier confinement while suppressing buffer-trap induced dispersion. Compared with conventional single-channel (SC) HEMTs, the DCGB HEMT exhibits an improved drain current (I

${}_{\mathrm {D}}$

) of approximately 0.3 A/mm. Current collapse is significantly reduced, as quantified by an improved post-stress recovery ratio (PSR

${}^{2}$

) of ~0.98 compared with ~0.80 in SC devices, corresponding to a reduction in current collapse of over 20%. This improvement is attributed to the formation of a volumetric three-dimensional electron gas (3DEG), which effectively screens the channel from Fe-related buffer trap charging. Transient drain-lag analysis further reveals faster recovery dynamics, with reduced trapping time constants extracted from exponential fitting of the transient response. These results provide design insight for dispersion-resilient GaN HEMTs targeting high-power RF, 6G power amplifier (PA), and space applications.

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缓冲陷阱诱导的第四系双通道梯度势垒algan /GaN hemt电流崩溃的缓解

本文采用数值模拟的方法，研究了双通道梯度势垒高电子迁移率晶体管（DCGB HEMT）的电流崩溃（CC）行为和可靠性改进。提出的DCGB结构增强了栅极静电控制和载流子约束，同时抑制了缓冲阱引起的色散。与传统的单通道HEMT相比，DCGB HEMT的漏极电流（I ${}_{\ mathm {D}}$）约为0.3 A/mm。与SC器件中的~0.80相比，SC器件的应力后恢复比（PSR ${}^{2}$）提高了~0.98，从而显著降低了电流崩溃，相当于电流崩溃降低了20%以上。这种改进归功于体积三维电子气体（3DEG）的形成，它有效地屏蔽了与铁相关的缓冲陷阱充电的通道。瞬态漏阻分析进一步揭示了更快的恢复动力学，从瞬态响应的指数拟合中提取了更少的捕获时间常数。这些结果为针对高功率射频、6G功率放大器（PA）和空间应用的色散弹性GaN hemt提供了设计见解。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Transactions on Device and Materials Reliability 工程技术-工程：电子与电气

CiteScore

4.80

自引率

5.00%

发文量

审稿时长

6-12 weeks

期刊介绍： The scope of the publication includes, but is not limited to Reliability of: Devices, Materials, Processes, Interfaces, Integrated Microsystems (including MEMS & Sensors), Transistors, Technology (CMOS, BiCMOS, etc.), Integrated Circuits (IC, SSI, MSI, LSI, ULSI, ELSI, etc.), Thin Film Transistor Applications. The measurement and understanding of the reliability of such entities at each phase, from the concept stage through research and development and into manufacturing scale-up, provides the overall database on the reliability of the devices, materials, processes, package and other necessities for the successful introduction of a product to market. This reliability database is the foundation for a quality product, which meets customer expectation. A product so developed has high reliability. High quality will be achieved because product weaknesses will have been found (root cause analysis) and designed out of the final product. This process of ever increasing reliability and quality will result in a superior product. In the end, reliability and quality are not one thing; but in a sense everything, which can be or has to be done to guarantee that the product successfully performs in the field under customer conditions. Our goal is to capture these advances. An additional objective is to focus cross fertilized communication in the state of the art of reliability of electronic materials and devices and provide fundamental understanding of basic phenomena that affect reliability. In addition, the publication is a forum for interdisciplinary studies on reliability. An overall goal is to provide leading edge/state of the art information, which is critically relevant to the creation of reliable products.