{"title":"Macro and Micro-Scale Non-Contact Imaging of Electrically Active Extended Defects in 4H-SiC Merged PiN Schottky Diode Devices","authors":"Firas Faisal;Nils Steller;Robin Karhu;Birgit Kallinger;Gennadi Polisski;Marshall Wilson;Alexandre Savtchouk;Liliana Gutierrez;Carlos Almeida;Cordero Soto;Bradley Wilson;Dmitriy Marinskiy;Adam Wincukiewicz;Jacek Lagowski","doi":"10.1109/TSM.2025.3614854","DOIUrl":null,"url":null,"abstract":"This study presents a novel approach to device yield estimation based on the non-contact, corona-based QUAD (Quality, Uniformity, and Defects) technique for inline defect mapping in SiC epitaxial layers. The approach is applied to a merged PiN Schottky (MPS) diode manufacturing process and is compared to final wafer-level electrical data. A new analysis method for QUAD defect mapping is introduced, incorporating die yield bin maps based on in-die depletion voltage values, allowing for a direct die to die comparison with standard EOL (End of the Line) electrical device testing. The QUAD mapping flow plan includes initial epi-wafers, the EOL wafers with measurement on metalized MPS dies, and the wafers after stripping off the metal. Micro-scale, <inline-formula> <tex-math>$\\mu $ </tex-math></inline-formula>QUAD depletion voltage maps resolving individual dies gives further insight into the nature of the device failures. Novel results show processing induced failures associated with defective electrical isolation of diodes. The unique yield-killing effects of clusters of stacking fault triangular defects are evidenced by a catastrophic breakdown voltage collapse and QUAD depletion voltage collapse in clusters of failed dies near the wafer edges. A strong correlation between the inline QUAD bin map results and final failed device maps highlights the potential of QUAD as a practical and powerful inline tool. This technique, achieving a 94% capture of failing MPS dies, offers a complementary approach to UVPL defect imaging, identifying electrical killer-defects and enhancing the yield estimations.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 4","pages":"744-749"},"PeriodicalIF":2.5000,"publicationDate":"2025-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Semiconductor Manufacturing","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/11182266/","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"2025/9/26 0:00:00","PubModel":"Epub","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
This study presents a novel approach to device yield estimation based on the non-contact, corona-based QUAD (Quality, Uniformity, and Defects) technique for inline defect mapping in SiC epitaxial layers. The approach is applied to a merged PiN Schottky (MPS) diode manufacturing process and is compared to final wafer-level electrical data. A new analysis method for QUAD defect mapping is introduced, incorporating die yield bin maps based on in-die depletion voltage values, allowing for a direct die to die comparison with standard EOL (End of the Line) electrical device testing. The QUAD mapping flow plan includes initial epi-wafers, the EOL wafers with measurement on metalized MPS dies, and the wafers after stripping off the metal. Micro-scale, $\mu $ QUAD depletion voltage maps resolving individual dies gives further insight into the nature of the device failures. Novel results show processing induced failures associated with defective electrical isolation of diodes. The unique yield-killing effects of clusters of stacking fault triangular defects are evidenced by a catastrophic breakdown voltage collapse and QUAD depletion voltage collapse in clusters of failed dies near the wafer edges. A strong correlation between the inline QUAD bin map results and final failed device maps highlights the potential of QUAD as a practical and powerful inline tool. This technique, achieving a 94% capture of failing MPS dies, offers a complementary approach to UVPL defect imaging, identifying electrical killer-defects and enhancing the yield estimations.
本研究提出了一种基于非接触、基于电晕的QUAD(质量、均匀性和缺陷)技术的器件良率估计新方法,用于SiC外延层的内联缺陷映射。该方法应用于合并PiN肖特基(MPS)二极管制造工艺,并与最终晶圆级电气数据进行了比较。介绍了一种新的QUAD缺陷映射分析方法,该方法结合了基于模内耗尽电压值的模具良率仓图,允许直接与标准EOL (End of the Line)电气设备测试进行模间比较。QUAD映射流程计划包括初始外延片、在金属化MPS模具上测量的EOL晶圆以及剥离金属后的晶圆。微尺度,$\mu $ QUAD耗尽电压图解决单个芯片,进一步深入了解器件故障的性质。新的结果表明,处理引起的故障与二极管的电气隔离缺陷有关。在靠近晶圆边缘的失效晶圆团簇中,灾难性击穿电压崩溃和QUAD耗尽电压崩溃证明了层错三角形缺陷团簇独特的产量杀伤效应。内联QUAD bin映射结果与最终失败的设备映射之间的强相关性突出了QUAD作为实用而强大的内联工具的潜力。该技术可捕获94%的MPS失效晶片,为UVPL缺陷成像提供了一种补充方法,可识别电气致命缺陷并提高良率估计。
期刊介绍:
The IEEE Transactions on Semiconductor Manufacturing addresses the challenging problems of manufacturing complex microelectronic components, especially very large scale integrated circuits (VLSI). Manufacturing these products requires precision micropatterning, precise control of materials properties, ultraclean work environments, and complex interactions of chemical, physical, electrical and mechanical processes.