{"title":"Multi-Scale Adaptive Inspection Framework for Voids in MOSFETs","authors":"Huankang Tang;Weibin Li;Jianghua Nie;Wenzhao Liang;Nian Cai;Jian Chen","doi":"10.1109/TSM.2025.3604212","DOIUrl":null,"url":null,"abstract":"During reflow soldering, Metal-Oxide- Semiconductor Field-Effect Transistors (MOSFETs) are prone to internal voids. A high void ratio for a MOSFET significantly affects its electrical performance to further decrease the reliability and lifespan of the electronic device. In this article, a multi-scale adaptive inspection framework is proposed to inspect internal voids in MOSFETs through X-ray imaging. First, a location-aware vertex detection scheme is utilized to detect the transistor region possibly involving the voids, which makes full advantages of the neighborhood grayscale distributions of the transistor region vertices. Then, after the detected transistor region is preprocessed and divided into several patches, coarse-to-fine void inspection is performed on the patches for void inspection. Specifically, a multi-scale scheme is proposed for coarse void inspection to identify whether the patches involve the potential voids, in which an identification function is defined by integrating the constructed multi-scale radial decaying weight matrix and a fitting metric to characterize the patches. An adaptive thresholding scheme is proposed to finely inspect the voids in the MOSFETs, in which the segmentation threshold model is constructed based on grayscale distributions of the MOSFET X-ray images. Finally, the void ratio is calculated according to the detected transistor and the voids. Experimental results indicate that the proposed framework achieves better inspection performance for voids in MOSFETs than some existing methods at the speed of 0.812s per MOSFET, with an average Dice of 0.8852, an Accuracy of 97.11%, and an F1-score of 0.9819.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 4","pages":"826-839"},"PeriodicalIF":2.5000,"publicationDate":"2025-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Semiconductor Manufacturing","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/11145236/","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"2025/8/29 0:00:00","PubModel":"Epub","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
During reflow soldering, Metal-Oxide- Semiconductor Field-Effect Transistors (MOSFETs) are prone to internal voids. A high void ratio for a MOSFET significantly affects its electrical performance to further decrease the reliability and lifespan of the electronic device. In this article, a multi-scale adaptive inspection framework is proposed to inspect internal voids in MOSFETs through X-ray imaging. First, a location-aware vertex detection scheme is utilized to detect the transistor region possibly involving the voids, which makes full advantages of the neighborhood grayscale distributions of the transistor region vertices. Then, after the detected transistor region is preprocessed and divided into several patches, coarse-to-fine void inspection is performed on the patches for void inspection. Specifically, a multi-scale scheme is proposed for coarse void inspection to identify whether the patches involve the potential voids, in which an identification function is defined by integrating the constructed multi-scale radial decaying weight matrix and a fitting metric to characterize the patches. An adaptive thresholding scheme is proposed to finely inspect the voids in the MOSFETs, in which the segmentation threshold model is constructed based on grayscale distributions of the MOSFET X-ray images. Finally, the void ratio is calculated according to the detected transistor and the voids. Experimental results indicate that the proposed framework achieves better inspection performance for voids in MOSFETs than some existing methods at the speed of 0.812s per MOSFET, with an average Dice of 0.8852, an Accuracy of 97.11%, and an F1-score of 0.9819.
期刊介绍:
The IEEE Transactions on Semiconductor Manufacturing addresses the challenging problems of manufacturing complex microelectronic components, especially very large scale integrated circuits (VLSI). Manufacturing these products requires precision micropatterning, precise control of materials properties, ultraclean work environments, and complex interactions of chemical, physical, electrical and mechanical processes.