RTL-to-Atoms Synthesis of a Machine Learning Accelerator on Atomic-Scale Computers

Abstract

As complementary metal-oxide-semiconductor (CMOS) scaling slows and artificial intelligence (AI) demand soars, atomic-scale platforms such as quantum-dot logic based on silicon dangling bond (SiDB) offer a promising path toward energy-efficient computation, yet practical design flows from register- transfer level (RTL) specifications to manufacturable layouts remain limited. This work presents an RTL-to-atoms synthesis framework for a quantized matrix multiply unit (MXU) targeting SiDB-based field-coupled nanocomputing (FCN). Building on recent advances in SiDB-aware electronic design automation (EDA), the framework combines a hierarchical, parameterized RTL architecture with platform-optimized arithmetic logic unit (ALU), reducing the synthesized logic core of processing elements by about $\bm {15\,\%}$ compared to prior flows. Key improvements were also made to the synthesis workflow to better optimize for SiDB logic and incorporate figure-of-merit awareness, which together ensure that the synthesized layouts achieve favorable area scaling and throughput while balancing operational robustness. Evaluations across multiple bit-widths show substantial footprint reductions for configurations within the tractable range of the latest placement-and-routing algorithms while preserving testbench-validated correctness from RTL to dot-accurate SiDB layouts, thereby establishing a reproducible benchmark for EDA on atomic-scale computing. This represents a significant milestone, bridging manually intensive workflows with scalable, automated methodologies, providing a valuable foundation for future design efforts for SiDB-based accelerators.