Hybrid Techniques for Power Noise Suppression on Multichip Packages

Abstract

Power-noise coupling among IPs is a common challenge in multichip-package (MCP) design. Voltage droop and power noise generated by an aggressor chiplet can couple to a victim chiplet through the power delivery network (PDN) on a shared power rail, particularly when the victim contains high-speed IP with stringent noise requirements. In conventional designs, coupling can be mitigated through PDN codesign and by adding board-level filtering for each chiplet. However, when the board design is frozen, noise observed on sensitive IP can become a gating item for package tape-out. This article presents three package- and die-level approaches for late-stage reduction of power-noise coupling between an aggressor and a victim. The first approach isolates PDN paths by partitioning the socket power-pin connectivity. The second approach integrates an embedded inductor to implement an in-package low-pass filter. The third approach optimizes on-die decoupling capacitance and effective resistance to attenuate high-frequency noise at the victim. Design and simulation were completed within two weeks of tape-out, demonstrating a 75% reduction in victim-rail noise.