{"title":"A Logic-Compatible 2-Transistor Embedded Bipolar RRAM MACRO: A 28-nm Multiple-Time Programmable (MTP) Memory Without Extra Masks","authors":"Yi Xiang Huang;Y. S. Lin;P. S. Huang;E. Ray Hsieh","doi":"10.1109/LSSC.2026.3675063","DOIUrl":null,"url":null,"abstract":"This letter presents a 2-transistor (2T) bipolar embedded resistive RAM (eRRAM) MACRO fabricated in a 28-nm high-k metal gate (HKMG) process for multitime programmable (MTP) applications. To overcome the scaling bottlenecks of traditional embedded Flash, this work utilizes an extra-mask-free, pure front-end-of-line (FEOL) integration, offering a robust solution for automotive and industrial SoCs at and beyond the 28-nm node. The unit cell architecture, read/write operations, and a low-power sense amplifier design are characterized. Experimental results for a 2-kb MACRO demonstrate 1000-cycle endurance with a sensing window over three-folds and data retention surpassing 1000 h at <inline-formula> <tex-math>$150~^{\\circ }$ </tex-math></inline-formula>C.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"9 ","pages":"117-120"},"PeriodicalIF":2.0000,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Solid-State Circuits Letters","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/11441410/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"2026/3/18 0:00:00","PubModel":"Epub","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0
Abstract
This letter presents a 2-transistor (2T) bipolar embedded resistive RAM (eRRAM) MACRO fabricated in a 28-nm high-k metal gate (HKMG) process for multitime programmable (MTP) applications. To overcome the scaling bottlenecks of traditional embedded Flash, this work utilizes an extra-mask-free, pure front-end-of-line (FEOL) integration, offering a robust solution for automotive and industrial SoCs at and beyond the 28-nm node. The unit cell architecture, read/write operations, and a low-power sense amplifier design are characterized. Experimental results for a 2-kb MACRO demonstrate 1000-cycle endurance with a sensing window over three-folds and data retention surpassing 1000 h at $150~^{\circ }$ C.