Characterization and Modeling of Multilevel Analog ReRAM Synapses in the Sky130 Process

Abstract

Nonvolatile memory devices play a key role in enabling energy-efficient computing. Among them, analog nonvolatile memories such as resistive random access memory (ReRAM) offer high density and low power compared to conventional digital memories. However, their analog nature introduces device-level variability that impacts computational accuracy. This work presents the characterization and compact modeling of ReRAM devices fabricated in the SkyWater 130-nm CMOS process. A two-transistor–one-ReRAM (2T–1R) structure is used to isolate individual cells and mitigate sneak-path currents. Each cell occupies $4.32~\mu \mathrm {m}^{2}$ , primarily determined by the access transistor sized for microampere-level currents. Statistical measurements are performed across multiple chips to quantify device-to-device variability and conductance distribution. Furthermore, a Verilog-A compact model is developed and calibrated to measured data, capturing nonlinear $I$ – $V$ behavior and variability for accurate circuit-level simulation. The resulting model enables reliable co-design of analog and neuromorphic systems that exploit ReRAM-based compute-in-memory (CIM) capabilities.