Monolithic Co-Integration of Vertical FET and Memristor for 1T1R Cell

Abstract

One-transistor-one-memristor (1T1R) structures are essential for large-scale memristor arrays, as they enable precise read and write operations for individual cells. Currently, most 1T1R designs employ planar field-effect transistors with laterally arranged source, drain, and channel, which limit the achievable array density within a planar layout. Here, we demonstrate a compact, vertically integrated 1T1R cell by stacking a MoS₂ vertical field-effect transistor (VFET) with a HfO₂ memristor. The VFET channel achieves a footprint of only 10 µm², which reduces reliance on advanced lithography and enables a reduced 1T1R cell area compared with some reported standard 0.18 µm silicon-based 1T1R implementations. The cell exhibits highly uniform resistive switching, with coefficients of variation (C_v) of only 3.4% in the high-resistance state (HRS) and 6.2% in the low-resistance state (LRS). Furthermore, it achieves quasi-linear conductance modulation across six discrete levels via VFET gate control. This demonstration establishes a scalable, area-efficient platform for 3D in-memory computing and neuromorphic structures.