An adaptive ant colony optimization-based obstacle-avoidance routing algorithm for Network-on-Chip

Abstract

Network-on-Chip (NoC) fault-tolerant routing presents substantial challenges in achieving an optimal balance among reliability, adaptability, and resource efficiency. Conventional approaches, such as dimension-ordered XY routing, lack dynamic fault-avoidance mechanisms, frequently resulting in congestion and packet loss upon encountering faulty nodes or links. Although bio-inspired algorithms, including Ant Colony Optimization (ACO), demonstrate potential for adaptive routing, current implementations inadequately integrate real-time fault awareness with congestion control while maintaining acceptable hardware overhead. To address these limitations, this paper introduces the Ant Colony Optimization-Fault-Aware (ACO-FA) routing mechanism, which incorporates dynamic path flexibility adaptation alongside buffer-state-aware congestion mitigation. The proposed approach employs a quantitative path flexibility model that dynamically modifies shortest paths through Manhattan distance corrections and fault-location awareness. Additionally, the Path Buffer Occupancy (PBO) metric quantifies multi-hop congestion risk, while a fault penalty factor ($\beta$) optimizes probabilistic path selection. Experimental evaluations indicate that ACO-FA surpasses conventional XY routing across multiple performance dimensions. Under various fault scenarios including single-node, dual-node, multi-node, and link failures, the proposed mechanism achieves improvements of up to 3.0% in Received/Ideal Flits Ratio, up to 30% in throughput at saturation, and up to 33% reduction in average latency.