Measurement and Analysis of Multistate Ferroelectric Transistors in 28 nm CMOS Process

Abstract

Ferroelectric field-effect transistors (FeFETs) are strong candidates for synaptic devices in neuromorphic and in-memory computing due to their multi-level programmability, non-volatility, and complementary metal-oxide-semiconductor (CMOS) compatibility. In this work, we experimentally demonstrate multi-bit operation of FeFET synapses integrated on GlobalFoundries’ 28nm CMOS process. Specifically, the work uses an incremental pulsing scheme, showing stable access to intermediate polarization states and long-term retention. We further examine the role of device size, read-out gate voltage, and array topology as fundamental design trade-offs, showing that larger-area FeFETs provide more deterministic state programming, while smaller devices favor integration density. Finally, we compare 1-FeFET and nT–1FeFET array architectures with static random-access memory (SRAM), outlining the density, selection, and scalability implications of each. These findings provide both device-level insights and circuit-architecture considerations, guiding the co-design of FeFET-based synaptic arrays for future neuromorphic accelerators.