Realization of Pure Boron/Si Diodes Through a Two-Step Low-Temperature Growth in a Home-Built LP CVD System

Abstract

For applications such as photodetection and electron microscopy, adopting ultra-shallow pn-junction diodes with ultra-low saturation currents is crucial. One way to realize such diodes is by employing an ultra-thin boron layer $\text {(}{\sim }2-10$ nm) on top of n-type silicon (Si), i.e., the boron/Si diode. So far, for relatively low process temperatures $\text {(}T\leq 400^{\circ }$ C) typically used in standard IC/CMOS processes, the boron/Si interface has not been formed in a controllable way. In this work, through an extensive in-depth growth study, we have developed a two-step growth method for the boron formation for a batch furnace, based on the assumption that the nucleation layer for growing boron is formed at $T=250^{\circ }$ C, and subsequently, a higher temperature $\text {(}T=400^{\circ }$ C) is used for a final rapid deposition of boron in a batch furnace. This approach enables precise control over the growth of thin boron layers. A long deposition at $250~^{\circ }$ C leads to the formation of a continuous boron layer, significantly reducing the surface roughness and lowering the incubation time at $T=400^{\circ }$ C. The improved boron coverage has a direct impact on the ideality factor $\text {(}\eta \text {)}$ and saturation current density $J_{\textrm {s}}$ , crucial for the boron/Si diode. As a result, for fully metallized structures a reproducibly low $J_{\textrm {s}}$ of $\sim 4.32\cdot 10^{-16}$ A/ $\mu $ m2 has been achieved, with an ideality factor of $\eta ~\approx ~1.02$ , and a barrier height $\Phi _{\textrm {B}}$ , i.e., a measure of the interface charge that induces the ultrashallow p+ layer, of ~0.84 V.