2 kV normally-off recessed p-NiO gate GaN-based HEMTs fabricated using “buffer-free” AlGaN/GaN heterostructures on SiC substrates

Abstract

The usage of p-NiO-based gate architecture can be beneficial over conventionally used p-GaN gate structure in the construction of normally-off GaN-based high electron mobility transistors, due to simpler, cost-effective and low-thermal budget fabrication process flow. Here in this work we report normally-off recessed p-NiO gate GaN-based HEMTs fabricated on "buffer-free" AlGaN/GaN heterostructure on 4H-SiC substrate. By using 17 nm recess p-NiO gate structure, appropriate post-deposition annealing and passivation scheme high positive threshold +0.8V (+0.2 V), high drain output current over 0.7 A/mm and low subthreshold swing 80 mV/dec and on-state resistance 10 Ωmm were obtained simultaneously. Thanks to the use of a high-quality heterostructure on a semi-insulating substrate and the absence of substrate leakage current, normally-off devices with high breakdown voltage values of up to 2 kV for a gate-drain distance of 20 μm were achieved, which corresponds to an average breakdown field value of 1 MV/cm, without the use of additional field-plate termination structures.