High-Speed I/O Equalizer Optimization Based on Deep Reinforcement Learning

Hung Khac Le;Jisoo Hwang;Jeong-Taek Kong;SoYoung Kim
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Abstract

In this work, we propose a signal integrity and power efficiency optimization framework for high-speed input/output equalizer systems using deep reinforcement learning based on a deep double Q-network. Although equalizer techniques have long existed, few studies have systematically optimized the feed-forward equalizer, decision feedback equalizer, and continuous-time linear equalizer together, including the high-speed channel properties. This framework determines the parameters of the equalizer architecture to optimize performance metrics such as eye height, eye width, and power consumption. It offers three key advantages: a framework with a scalable deep neural network to efficiently model complex design challenges; a future-state technique that mitigates design-space expansion with a minimum number of output neurons; and simultaneous evaluation of power efficiency, unachievable with conventional methods. As a proof of concept, we present the optimization of equalizer architecture using the proposed approach across different high-speed channels, including a backplane and an interference-tolerant channel. Experimental results demonstrate that our approach improves signal and power performance significantly compared to those from conventional methods (e.g., minimum-mean squared error and least-mean squared) and converges much faster than genetic, particle swarm, and Bayesian optimization algorithms.
基于深度强化学习的高速I/O均衡器优化
在这项工作中,我们提出了一个基于深度双q网络的深度强化学习的高速输入/输出均衡器系统的信号完整性和功率效率优化框架。虽然均衡器技术早已存在,但很少有研究将前馈均衡器、判决反馈均衡器和连续时间线性均衡器一起系统地优化,包括高速信道特性。该框架确定均衡器架构的参数,以优化眼高、眼宽和功耗等性能指标。它提供了三个关键优势:一个具有可扩展深度神经网络的框架,可以有效地模拟复杂的设计挑战;一种未来状态技术,以最小的输出神经元数量减轻设计空间的扩展;同时评估电源效率,这是传统方法无法实现的。作为概念验证,我们提出了均衡器架构的优化,使用所提出的方法跨不同的高速通道,包括背板和干扰容忍通道。实验结果表明,与传统方法(如最小均方误差和最小均方误差)相比,我们的方法显著提高了信号和功率性能,并且比遗传、粒子群和贝叶斯优化算法收敛得快得多。
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