Evaluation of a single interface trap position on the low-frequency noise of junctionless nanowire transistors

Abstract

This work investigates the impact of key operating parameters on the low-frequency noise (LFN) of experimental and simulated junctionless nanowire transistors. The primary goal was to vary the gate-to-source voltage (V_GS) at a low drain-to-source voltage (V_DS) to observe its direct effect on the current noise spectral density (S_id), as this provides crucial insights into the characteristics of predominant traps. The noise was measured by shifting the source and drain terminals, aiming to verify the influence of the dominant traps’ position on the noise. The S_id extractions were performed using a Keysight B1500 with an SR560 amplifier and an HP4395 spectrum analyzer. The analysis was supported by 3D numerical simulations of structures considering a single dominant trap center. The main results show a clear trend of increasing S_id with higher V_GS, although this is affected in short-channel devices. Most importantly, the trap location was confirmed to be a critical factor, demonstrating distinct S_id trends when traps are closer to the source with respect to the drain, a behavior also impacted by short-channel effects (SCEs).