A Bit-Cell Failure Analysis Framework for Ferroelectric Field-Effect Transistor-Based Memories

Abstract

The ferroelectric field-effect transistor (FeFET) is a promising memory device technology due to desirable attributes, such as fast access times, high memory cell density, good endurance, compatibility with CMOS process, and impressive scalability. While previous research has explored the impact of process variations at the device level, their effects on circuit behavior have not been comprehensively investigated due to a lack of a framework for analyzing FeFET bit-cell failures at the circuit level, which we present in this work. We studied the process parameters, including ferroelectric (FE) layer thickness, channel length, channel width, and effective oxide thickness of an FeFET bit cell. The correlations of each failure event and the write pulse voltage and write pulsewidth are studied. Our results show that the voltage applied on the FeFET bit cell dominates the performance of the bit cell for both write and read operations.