Power-Balanced Memristive Cryptographic Implementation Against Side Channel Attacks

Abstract

Memristors, as emerging nano-devices, offer promising performance and exhibit rich electrical dynamic behavior. Having already found success in applications such as neuromorphic and in-memory computing, researchers are now exploring their potential for cryptographic implementations. In this study, we present a novel power-balanced hiding strategy utilizing memristor groups to conceal power consumption in cryptographic logic circuits. Our approach ensures consistent power costs of all 16 logic gates in Complementary-Resistive-Switching-with-Reading (CRS-R) logic family during writing and reading cycles regardless of Logic Input Variable (LIV) values. By constructing hiding groups, we enable an effective power balance in each gate hiding group. Furthermore, experimental validation of our strategy includes the implementation of a cryptographic construction, xor4SBox, using hiding groups containing NOR gates. The circuit construction without the hiding strategy and with the hiding strategy undergo Test Vector Leakage Assessment (TVLA) based on T-test, confirming the significant improvement achieved with our approach. To address the extensive data requirements necessitated by the T-test, simulated power traces are employed. Our work presents a substantial advancement in power-balanced hiding methods, offering enhanced security and efficiency in logic circuits.