Beyond Backside Power: Backside Signal Routing as Technology Booster for Standard-Cell Scaling

Abstract

Advances in process technology enabling backside metals (BSMs) and contacts offer new design–technology co-optimization (DTCO) opportunities to further enhance power, performance, and area gains (PPA) in sub-3-nm nodes. This work exploits backside (BS) contact technology within standard cells to extend both signal and clock routing to BSM layers, enabling standard-cell height reduction options. We design electrically equivalent (EEQ) standard cells with multiple layout variants based on front versus BS pin access, achieving a 2-M0-Track height reduction in 3-nm gate-all-around field-effect transistor (GAAFET) technology. Experimental evaluation across representative industrial benchmarks—including high-performance CPUs, GPUs, and general-purpose systems-on-chip (SoCs) demonstrates significant benefits. Cell height reduction delivers up to 35% area savings and 10%–15% total power reduction for GPU and GP-SoC designs. For high-performance CPUs, maximum performance improves by 15% at iso-power compared to backside power with buried power rails (BSBPR). Incorporating BS signal routing with cell height reduction also reduces worst case IR drop by 32% relative to BSBPR. These results show that BS clock (BSCLK) and signal routing represent the next phase of technology innovation beyond BS power delivery, enabling continued standard-cell scaling, improved intracell and intercell routability, and generational PPA gains while maintaining similar core transistor geometries in sub-3-nm technologies.