A Benchmark of Cryo-CMOS Dynamic Comparators in a 40 nm Bulk CMOS Technology

Abstract

All cryo-CMOS quantum-classical control interfaces require an analog-to-digital converter (ADC) bridging the analog qubits and the digital control logic. Dynamic comparators play a crucial role in the precision, speed, and power consumption of these ADCs. Yet, their performance is severely impacted by the cryogenic environment. Therefore, this letter benchmarks, for the first time in the literature, four comparator topologies at room temperature (RT) and 6K. Their noise, delay, and energy consumption are characterized, allowing the identification of the best topology for a given application. This analysis shows that the strongARM (SA) comparator is the most energy efficient, closely followed by the double tail comparator. However, the reduced voltage headroom at 6K almost doubles the SA’s delay compared to RT and leaves it susceptible to common-mode and supply voltage variations. In contrast, the recently proposed triple tail comparator with capacitive over-neutralization limits the delay increase to only 13ps by separating the preamplifier and the latch. Furthermore, its boosted preamplification gain makes it notably more resilient to voltage variations, ensuring a highly robust cryogenic operation favorable for scaled technologies.