A 168 nW to 44.3 Mb/s Adaptable TRNG With 400 mV Attack-Resilient Hybrid RO Core

IF 2 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Solid-State Circuits Letters Pub Date : 2025-10-14 DOI:10.1109/LSSC.2025.3621413

Berkay Özbek;Timothy G. Constandinou

{"title":"A 168 nW to 44.3 Mb/s Adaptable TRNG With 400 mV Attack-Resilient Hybrid RO Core","authors":"Berkay Özbek;Timothy G. Constandinou","doi":"10.1109/LSSC.2025.3621413","DOIUrl":null,"url":null,"abstract":"This letter presents an adaptable ring oscillator (RO)-true random number generator (TRNG) that removes the fixed power–throughput tradeoff by selecting delay-cell physics at run time. A hybrid core uses a current-starved inverter in low-power (LP) mode to amplify slew-limited jitter for high bit-efficiency at low frequency, and a latched cross-coupled cell in high-performance (HP) mode to exploit regeneration-time jitter over a wider band; both share a unified fast-by-slow sampling path with XOR combining. Fabricated in 180 nm CMOS (<inline-formula> <tex-math>$265\\times 490~\\mu $ </tex-math></inline-formula>m), the TRNG spans 0.8–2.0 V and <inline-formula> <tex-math>$- 20~^{\\circ }$ </tex-math></inline-formula>C–<inline-formula> <tex-math>$80~^{\\circ }$ </tex-math></inline-formula>C, achieves 168 nW (3.95 pJ/bit) in LP and 44.3 Mb/s in HP, and reaches near-ideal HP entropy (0.999999999984). Long datasets pass NIST SP 800-22 (including under 400 mV injection at the second harmonic), SP 800-90B, and AIS31. A single, digitally-tunable IP thus delivers nanowatt standby entropy and burst-mode throughput without architectural change.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"8 ","pages":"325-328"},"PeriodicalIF":2.0000,"publicationDate":"2025-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Solid-State Circuits Letters","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/11202908/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}

引用次数: 0

Abstract

This letter presents an adaptable ring oscillator (RO)-true random number generator (TRNG) that removes the fixed power–throughput tradeoff by selecting delay-cell physics at run time. A hybrid core uses a current-starved inverter in low-power (LP) mode to amplify slew-limited jitter for high bit-efficiency at low frequency, and a latched cross-coupled cell in high-performance (HP) mode to exploit regeneration-time jitter over a wider band; both share a unified fast-by-slow sampling path with XOR combining. Fabricated in 180 nm CMOS (

$265\times 490~\mu $

m), the TRNG spans 0.8–2.0 V and

$- 20~^{\circ }$

C–

$80~^{\circ }$

C, achieves 168 nW (3.95 pJ/bit) in LP and 44.3 Mb/s in HP, and reaches near-ideal HP entropy (0.999999999984). Long datasets pass NIST SP 800-22 (including under 400 mV injection at the second harmonic), SP 800-90B, and AIS31. A single, digitally-tunable IP thus delivers nanowatt standby entropy and burst-mode throughput without architectural change.

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一个168 nW到44.3 Mb/s的可适应TRNG，带有400 mV抗攻击的混合RO核心

本文介绍了一种自适应环振荡器(RO)-真随机数发生器（TRNG），它通过在运行时选择延迟单元物理来消除固定的功率吞吐量权衡。混合核心在低功耗（LP）模式下使用电流匮乏的逆变器来放大slew-limited抖动，以实现低频下的高比特效率，在高性能（HP）模式下使用锁存交叉耦合单元来利用更宽频带上的再生时间抖动；两者共享一个统一的快慢采样路径与异或组合。在180 nm CMOS （$265\times 490~\mu $ m）上制造，TRNG跨越0.8-2.0 V和$- 20~^{\circ}$ C - $80~^{\circ}$ C，在LP中达到168 nW (3.95 pJ/bit)，在HP中达到44.3 Mb/s，并达到接近理想的HP熵（0.999999999984）。长数据集通过NIST SP 800-22（包括二次谐波注入低于400 mV）， SP 800-90B和AIS31。一个单一的，数字可调的IP因此提供纳瓦待机熵和突发模式吞吐量，而无需架构更改。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Solid-State Circuits Letters Engineering-Electrical and Electronic Engineering

CiteScore

4.30

自引率

3.70%

发文量