An N-type JTE assisted field ring termination for 1200 V SiC MOSFET with increased reliability robustness

IF 4.6 3区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Materials Science in Semiconductor Processing Pub Date : 2025-10-18 DOI:10.1016/j.mssp.2025.110162

Mengyuan Yu , Qingchun Jon Zhang

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引用次数: 0

Abstract

Field limited ring (FLR) technique is widely used in silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) and junction barrier Schottky (JBS) edge termination design due to its easy to process and low fabrication cost. However, traditional FLR structure is very sensitive to surface charge variance during device operation, especially in reliability test, which will cause termination degradation. In this paper, an N-type junction termination extension (JTE) assisted FLR structure is proposed to solve the problem. Compared with traditional FLR termination, by adding an N-type JTE implantation, the electric field is alleviated under wide range of surface charge, thus significantly reduces the breakdown voltage (BV) sensitivity to surface charge. In addition, the new structure can also reduce electric field strength of field oxide in termination area, thus increases device robustness in humidity reliability test. Both TCAD simulation and experiment results show the proposed structure can effectively improve device reliability.

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一种用于1200 V SiC MOSFET的n型JTE辅助场环终端，可靠性增强

场限环（FLR）技术因其易于加工和制造成本低而广泛应用于碳化硅（SiC）金属氧化物半导体场效应晶体管（MOSFET）和结势垒肖特基（JBS）边缘终端设计中。然而，传统的FLR结构在器件运行过程中，特别是在可靠性测试中，对表面电荷变化非常敏感，会导致终端性能下降。本文提出了一种n型结终端扩展（JTE）辅助FLR结构来解决这一问题。与传统的FLR终端相比，通过添加n型JTE注入，在宽表面电荷范围内电场得到缓解，从而显著降低击穿电压（BV）对表面电荷的敏感性。此外，新结构还可以降低端接区场氧化物的电场强度，从而提高器件在湿度可靠性试验中的稳健性。TCAD仿真和实验结果均表明，该结构能有效提高器件的可靠性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Materials Science in Semiconductor Processing 工程技术-材料科学：综合

CiteScore

8.00

自引率

4.90%

发文量

780

审稿时长

42 days

期刊介绍： Materials Science in Semiconductor Processing provides a unique forum for the discussion of novel processing, applications and theoretical studies of functional materials and devices for (opto)electronics, sensors, detectors, biotechnology and green energy. Each issue will aim to provide a snapshot of current insights, new achievements, breakthroughs and future trends in such diverse fields as microelectronics, energy conversion and storage, communications, biotechnology, (photo)catalysis, nano- and thin-film technology, hybrid and composite materials, chemical processing, vapor-phase deposition, device fabrication, and modelling, which are the backbone of advanced semiconductor processing and applications. Coverage will include: advanced lithography for submicron devices; etching and related topics; ion implantation; damage evolution and related issues; plasma and thermal CVD; rapid thermal processing; advanced metallization and interconnect schemes; thin dielectric layers, oxidation; sol-gel processing; chemical bath and (electro)chemical deposition; compound semiconductor processing; new non-oxide materials and their applications; (macro)molecular and hybrid materials; molecular dynamics, ab-initio methods, Monte Carlo, etc.; new materials and processes for discrete and integrated circuits; magnetic materials and spintronics; heterostructures and quantum devices; engineering of the electrical and optical properties of semiconductors; crystal growth mechanisms; reliability, defect density, intrinsic impurities and defects.