Engineering oxygen precipitation for simultaneous denuded zone and bulk microdefect formation in pre-annealed heavily boron-doped Czochralski silicon substrates for p/p+ epitaxial wafers

IF 4.6 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC
Jinge Wang , Yilun Wang , Tong Zhao , Yuna Yin , Pengfei Gao , Tiebo Zheng , Xingbo Liang , Daxi Tian , Deren Yang , Xiangyang Ma
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引用次数: 0

Abstract

Heavily boron-doped Czochralski (HB-Cz) silicon substrates (10–20 mΩ·cm) for p/p+ epitaxial wafers face difficulty in simultaneously forming an oxide-precipitate-free denuded zone (DZ) and a high-density bulk microdefect (BMD) zone during device thermal processing, due to oxygen precipitation enhanced by the heavy boron-doping. The as-received HB-Cz silicon substrates, whether from the seed-end or the tail-end of the silicon crystal ingot, fail to simultaneously form both a DZ and a high-density BMD zone after the simulated device thermal processing (780 °C/3 h + 1000 °C/16 h, L-H annealing) of the corresponding epitaxial wafers. This work investigates the pre-annealing processes involving rapid thermal annealing (RTA), conventional furnace annealing (CFA), and their combinations for HB-Cz silicon substrates to address the aforementioned technical dilemma. As a result, we establish a dedicated pre-annealing process: the non-interchangeable, sequential application of RTA (1250 °C/30 s, cooling rate: 25–100 °C/s) and CFA (1200 °C/3 h, ramping-up from 700 to 1200 °C at 5 °C/min). The RTA step dissolves the grown-in oxide precipitates and introduces the vacancy-oxygen (VOm, m ≤ 4) complexes into the bulk region of substrate, serving as the heterogeneous nucleation precursors for oxygen precipitation during the subsequent CFA step, while occurring vacancy out-diffusion near the surface of substrate to facilitate DZ formation. The subsequent CFA step enables the oxide precipitate nucleation and growth based on the RTA-induced VOm complexes, while simultaneously promoting the oxygen out-diffusion to secure the DZ width. The optimized RTA + CFA pre-annealing process, ensures both a well-defined DZ (>40 μm) and high-density BMDs in HB-Cz silicon substrates from any crystal ingot position after the L-H annealing of corresponding p/p+ epitaxial wafers. Therefore, this RTA + CFA pre-annealing strategy provides a robust and universal technical foundation for manufacturing high-performance p/p+ epitaxial wafers essential for advanced power devices and integrated circuits.
在p/p+外延片中预退火重掺硼直拉基硅衬底中同时形成剥蚀区和大块微缺陷的工程氧沉淀
在p/p+外延片中,重硼掺杂的chzochralski (HB-Cz)硅衬底(10-20 mΩ·cm)在器件热加工过程中,由于重硼掺杂增强了氧析出,难以同时形成无氧化物析出区(DZ)和高密度体微缺陷(BMD)区。在对相应外延片进行模拟器件热处理(780°C/3 h + 1000°C/16 h, L-H退火)后,接收到的HB-Cz硅衬底,无论是来自硅晶锭的种子端还是硅晶锭的尾端,都无法同时形成DZ和高密度BMD区。本研究研究了HB-Cz硅衬底的预退火工艺,包括快速热退火(RTA)、传统炉退火(CFA)及其组合,以解决上述技术难题。因此,我们建立了专用的预退火工艺:不可互换的顺序应用RTA(1250°C/30 s,冷却速度:25-100°C/s)和CFA(1200°C/3 h,从700°C上升到1200°C, 5°C/min)。RTA步骤溶解生长的氧化物沉淀,并将空位-氧(VOm, m≤4)配合物引入底物的体区,作为后续CFA步骤中氧沉淀的非均相成核前体,同时在底物表面附近发生空位向外扩散,促进DZ的形成。随后的CFA步骤使氧化物沉淀基于rta诱导的VOm配合物的成核和生长,同时促进氧向外扩散以确保DZ宽度。经过优化的RTA + CFA预退火工艺,可确保在相应的p/p+外延片经过L-H退火后,在HB-Cz硅衬底的任何晶锭位置都具有明确的DZ (>40 μm)和高密度的bmd。因此,这种RTA + CFA预退火策略为制造先进功率器件和集成电路所需的高性能p/p+外延片提供了强大而通用的技术基础。
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来源期刊
Materials Science in Semiconductor Processing
Materials Science in Semiconductor Processing 工程技术-材料科学:综合
CiteScore
8.00
自引率
4.90%
发文量
780
审稿时长
42 days
期刊介绍: Materials Science in Semiconductor Processing provides a unique forum for the discussion of novel processing, applications and theoretical studies of functional materials and devices for (opto)electronics, sensors, detectors, biotechnology and green energy. Each issue will aim to provide a snapshot of current insights, new achievements, breakthroughs and future trends in such diverse fields as microelectronics, energy conversion and storage, communications, biotechnology, (photo)catalysis, nano- and thin-film technology, hybrid and composite materials, chemical processing, vapor-phase deposition, device fabrication, and modelling, which are the backbone of advanced semiconductor processing and applications. Coverage will include: advanced lithography for submicron devices; etching and related topics; ion implantation; damage evolution and related issues; plasma and thermal CVD; rapid thermal processing; advanced metallization and interconnect schemes; thin dielectric layers, oxidation; sol-gel processing; chemical bath and (electro)chemical deposition; compound semiconductor processing; new non-oxide materials and their applications; (macro)molecular and hybrid materials; molecular dynamics, ab-initio methods, Monte Carlo, etc.; new materials and processes for discrete and integrated circuits; magnetic materials and spintronics; heterostructures and quantum devices; engineering of the electrical and optical properties of semiconductors; crystal growth mechanisms; reliability, defect density, intrinsic impurities and defects.
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