Post-fab porous silicon in silicon-on-insulator substrates for improved radio frequencies performances

Abstract

This article presents a new post-fabrication (post-fab) porous silicon (PSi) integration process adapted to standard-resistivity silicon handle substrates (10–20 Ω⋅cm). The process enables uniform porosification from the wafer backside through to an etch-stop layer beneath the buried oxide (BOX). This process does not involve the frontside and does not exceed 150 °C, ensuring full compatibility with previously fabricated devices. A metallic grid ensures homogeneous current distribution, overcoming the conductivity limitations of standard-resistivity substrates compared to the usual low resistivity substrates used for porous silicon integration. Coplanar waveguides lines are fabricated as test structures, and radio frequency measurements confirm excellent performance, including low permittivity (ϵ_r,eff = 4.3 at 5 GHz), high effective resistivity (>3 kΩ⋅cm at 5 GHz), and low harmonic distortion (H2 = −115 dBm at H1 = 15 dBm). This work demonstrates that post-fab PSi integration can be achieved on CMOS-compatible standard substrates, eliminating contamination risks present with highly doped substrates and making porous silicon integration more straightforward in industrial applications.