{"title":"An Ultra-Low Power 1.2 pJ/Spike Fully CMOS Spiking Neuron and Its Application","authors":"Prashant Kumar;Rajeev Kumar Ranjan;Sung-Mo Kang","doi":"10.1109/TNANO.2025.3613362","DOIUrl":null,"url":null,"abstract":"Electronic neurons, such as integrate-and-fire models and memristor synapses, are key components of energy-efficient spiking neural network (SNN) systems. Current silicon-based models face challenges due to high transistor counts, large footprints, and excessive energy consumption. This brief presents a low-transistor count, energy-efficient neuron design. Our spiking signal-generating circuit consumes approximately 1.2 pJ per spike and uses a single capacitor as its only passive element, while occupying a layout area of 66.93 <inline-formula><tex-math>$\\mathrm{\\mu }$</tex-math></inline-formula>m × 36.12 <inline-formula><tex-math>$\\mathrm{\\mu }$</tex-math></inline-formula>m and operating on a 1 V power supply. We also highlight the driving capability and pattern recognition application of our proposed neuron model.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"462-468"},"PeriodicalIF":2.1000,"publicationDate":"2025-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Nanotechnology","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/11176826/","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
Electronic neurons, such as integrate-and-fire models and memristor synapses, are key components of energy-efficient spiking neural network (SNN) systems. Current silicon-based models face challenges due to high transistor counts, large footprints, and excessive energy consumption. This brief presents a low-transistor count, energy-efficient neuron design. Our spiking signal-generating circuit consumes approximately 1.2 pJ per spike and uses a single capacitor as its only passive element, while occupying a layout area of 66.93 $\mathrm{\mu }$m × 36.12 $\mathrm{\mu }$m and operating on a 1 V power supply. We also highlight the driving capability and pattern recognition application of our proposed neuron model.
期刊介绍:
The IEEE Transactions on Nanotechnology is devoted to the publication of manuscripts of archival value in the general area of nanotechnology, which is rapidly emerging as one of the fastest growing and most promising new technological developments for the next generation and beyond.