An Ultra-Low Power 1.2 pJ/Spike Fully CMOS Spiking Neuron and Its Application

IF 2.1 4区 工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC
Prashant Kumar;Rajeev Kumar Ranjan;Sung-Mo Kang
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引用次数: 0

Abstract

Electronic neurons, such as integrate-and-fire models and memristor synapses, are key components of energy-efficient spiking neural network (SNN) systems. Current silicon-based models face challenges due to high transistor counts, large footprints, and excessive energy consumption. This brief presents a low-transistor count, energy-efficient neuron design. Our spiking signal-generating circuit consumes approximately 1.2 pJ per spike and uses a single capacitor as its only passive element, while occupying a layout area of 66.93 $\mathrm{\mu }$m × 36.12 $\mathrm{\mu }$m and operating on a 1 V power supply. We also highlight the driving capability and pattern recognition application of our proposed neuron model.
超低功耗1.2 pJ/Spike全CMOS Spike神经元及其应用
电子神经元,如集成-放电模型和忆阻突触,是节能尖峰神经网络(SNN)系统的关键组成部分。目前基于硅的模型面临着挑战,由于高晶体管数量,大足迹,和过度的能源消耗。本简报介绍一种低晶体管数、高能效的神经元设计。我们的尖峰信号产生电路每个尖峰消耗约1.2 pJ,并使用单个电容器作为其唯一的无源元件,而占用的布局面积为66.93 $\ mathm {\mu}$m × 36.12 $\ mathm {\mu}$m,工作在1v电源上。我们还强调了我们所提出的神经元模型的驱动能力和模式识别应用。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
IEEE Transactions on Nanotechnology
IEEE Transactions on Nanotechnology 工程技术-材料科学:综合
CiteScore
4.80
自引率
8.30%
发文量
74
审稿时长
8.3 months
期刊介绍: The IEEE Transactions on Nanotechnology is devoted to the publication of manuscripts of archival value in the general area of nanotechnology, which is rapidly emerging as one of the fastest growing and most promising new technological developments for the next generation and beyond.
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