An FPGA-based architecture for time-resolved polarization probing of FeRAM fatigue

Abstract

Traditional approaches to assessing Ferroelectric RAM (FeRAM) reliability rely on direct electrical access to individual capacitors. While effective on isolated test structures, such methods are infeasible for high-density, packaged memory arrays, creating a critical gap between device-level physics and system-level reliability assessment. To bridge this gap, we propose Time-Resolved Polarization Probing (TRPP), a novel indirect methodology that infers the internal polarization state by precisely measuring the minimum switching time accessible at the cell terminals. We implement TRPP on a custom FPGA-based platform that integrates a flexible MBIST engine for controlled fatigue stressing with a carry-chain programmable delay generator offering 53 ps resolution. Experimental results on FeRAM devices demonstrate that TRPP effectively quantifies the progressive degradation of polarization kinetics under stress up to $10^9$ cycles. The measurements further reveal disproportionately severe degradation at lower operating voltages, underscoring critical implications for low-power and compute-in-memory applications. Overall, this work establishes TRPP as a high-resolution, scalable methodology for reliability characterization, bridging the gap between device physics and system-level deployment.