5-nm High-Efficiency and High-Density Digital SRAM In-Memory-Computing Macros for AI Accelerators

Abstract

Two specialized digital SRAM In-memory computing (IMC) macros were implemented using a 5-nm process: 1) a high efficiency (HE) macro and 2) a high-density (HD) macro. The HE macro achieves an energy efficiency of 274 TOPS/W under 90% input bit sparsity, 50% weight bit sparsity, and 0.46-V supply voltage, by adopting a compact Wallace tree adder (WTA) and a tristate buffer optimized for pipelined operation. The HD macro achieves a state-of-the-art memory density performance of 5.67 Mb/mm2 by employing a multiply-cell consisting of a single transistor. Extensive sample measurements have confirmed the robust and reliable performance of the two digital IMC macros. The proposed HE and HD macros have demonstrated their significant potential as key building blocks for next-generation Artificial intelligence (AI) accelerators.