Reducing Warpage for Polymer-Based Embedded Silicon Fan-Out (P-eSiFO) Packaging During Thermal Process Loadings

IF 3 3区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2025-06-09 DOI:10.1109/TCPMT.2025.3578042

Jianyu Du;Lang Chen;Han Xu;Jinwen Zhang;Huaiqiang Yu;Chi Zhang;Wei Wang

{"title":"Reducing Warpage for Polymer-Based Embedded Silicon Fan-Out (P-eSiFO) Packaging During Thermal Process Loadings","authors":"Jianyu Du;Lang Chen;Han Xu;Jinwen Zhang;Huaiqiang Yu;Chi Zhang;Wei Wang","doi":"10.1109/TCPMT.2025.3578042","DOIUrl":null,"url":null,"abstract":"Polymer-based embedded silicon-based fan-out (P-eSiFO) is a new packaging technique, which provides a way to high-density integration of high-performance chiplets. However, integrating multiple materials with diverse physical properties in the P-eSiFO leads to substantial warpage during downstream high-temperature manufacturing processes. In this study, a thermomechanical model of a P-eSiFO was developed to examine the thermomechanical with varying structural parameters and material selections. Test dies having an area of 0.5 cm<sup>2</sup> were embedded in a 500-<inline-formula> <tex-math>$\\mu $ </tex-math></inline-formula>m-thick silicon carrier following the P-eSiFO process. After careful parameters, optimization chip warpage can effectively decrease by over 60%. Experimental results showed that the height difference between the embedded chip and its silicon interposer can be reduced down to <inline-formula> <tex-math>$1~\\mu $ </tex-math></inline-formula>m with optimized parameters after high-temperature processes. This work provides useful insights for addressing multimaterial warpage concerns during thermal processes in advanced packaging.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 9","pages":"2033-2040"},"PeriodicalIF":3.0000,"publicationDate":"2025-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Components, Packaging and Manufacturing Technology","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/11029086/","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}

引用次数: 0

Abstract

Polymer-based embedded silicon-based fan-out (P-eSiFO) is a new packaging technique, which provides a way to high-density integration of high-performance chiplets. However, integrating multiple materials with diverse physical properties in the P-eSiFO leads to substantial warpage during downstream high-temperature manufacturing processes. In this study, a thermomechanical model of a P-eSiFO was developed to examine the thermomechanical with varying structural parameters and material selections. Test dies having an area of 0.5 cm² were embedded in a 500-

$\mu $

m-thick silicon carrier following the P-eSiFO process. After careful parameters, optimization chip warpage can effectively decrease by over 60%. Experimental results showed that the height difference between the embedded chip and its silicon interposer can be reduced down to

$1~\mu $

m with optimized parameters after high-temperature processes. This work provides useful insights for addressing multimaterial warpage concerns during thermal processes in advanced packaging.

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减少聚合物基嵌入式硅扇出（P-eSiFO）封装在热加工加载过程中的翘曲

基于聚合物的嵌入式硅基扇出（P-eSiFO）是一种新型封装技术，为高性能小芯片的高密度集成提供了途径。然而，在P-eSiFO中集成具有不同物理特性的多种材料会在下游高温制造过程中导致大量翘曲。在这项研究中，建立了P-eSiFO的热力学模型，以研究不同结构参数和材料选择下的热力学。按照P-eSiFO工艺，将面积为0.5 cm2的测试模具嵌入500- $\mu $ m厚的硅载体中。经过精心的参数设计，优化后的芯片翘曲率可有效降低60%以上。实验结果表明，经高温处理后，优化后的工艺参数可使芯片与硅中间层之间的高度差减小到$1~ $ μ $ m。这项工作提供了有用的见解，解决多材料翘曲问题在热过程中的先进封装。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Transactions on Components, Packaging and Manufacturing Technology ENGINEERING, MANUFACTURING-ENGINEERING, ELECTRICAL & ELECTRONIC

CiteScore

4.70

自引率

13.60%

发文量

203

审稿时长

3 months

期刊介绍： IEEE Transactions on Components, Packaging, and Manufacturing Technology publishes research and application articles on modeling, design, building blocks, technical infrastructure, and analysis underpinning electronic, photonic and MEMS packaging, in addition to new developments in passive components, electrical contacts and connectors, thermal management, and device reliability; as well as the manufacture of electronics parts and assemblies, with broad coverage of design, factory modeling, assembly methods, quality, product robustness, and design-for-environment.