Resistive Defect Analysis and Fault Modeling of DICE Memory in Commercial 40-nm CMOS Technology

Abstract

The complex architecture of double interlocked storage cell (DICE) static random access memories (SRAM), which consists of 12 Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), presents challenges in manufacturing test. Manufacturing defects can cause faults in DICE SRAMs, and undetected faults may lead to test escapes, resulting in early in-field failures. These issues can prevent DICE SRAMs from meeting the applications requiring high quality in sectors such as aerospace. This paper proposes a new type of SEU fault for DICE SRAM, analyzing how physical defects influence its SEU resilience, which forms a new fault space together with parameter faults and functional faults.This paper presents a detailed analysis and fault modeling of resistive defects that may occur in DICE SRAMs and proposes a novel test algorithm to enhance fault coverage and reduce test escapes during manufacturing test. First, we define and classify the fault space, including functional faults, parameter faults, and single event upset (SEU) faults, and outline the methodology to validate faults within this space. Next, we inject resistive defects into the SPICE netlist of DICE SRAMs, conduct SPICE simulation, and inspect its corresponding behavior. Furthermore, through the analysis of the fault modeling results of DICE SRAMs and evaluating the test coverage and limitations of existing test solutions, we propose a new test algorithm. This results in a substantial increase in dynamic fault coverage from 20.57% to 28.37% and an overall improvement in fault coverage from 33.88% to 39.89% when compared to the March C+ algorithm, while reducing the possibility of test escape for parameter faults (including HSNM and RSNM faults) and SEU faults. In summary, the findings of the paper are effective in detecting the realistic faults in DICE SRAMs, thereby bolstering the effectiveness of DICE SRAMs test for critical applications.