Evaluation of BTI Lifetime for MOSFETs in 55 nm CMOS Node by 1/f Noise Performance Degradation

Abstract

In this study, the bias temperature instability (BTI) degradation of Si p- and n-MOSFETs fabricated using a 55 nm CMOS process was systematically and quantitatively investigated over stress time $(T_{stress})$ . This analysis focused on key parameters, including threshold voltage shift $(\Delta V_{th})$ , subthreshold swing degradation ( $\Delta $ SS), maximum transconductance reduction ( $\Delta Gm_{max}$ ), linear region current decrease $(\Delta I_{dlin})$ , and 1/f noise performance degradation. By examining the dependence of these parameters on $T_{stress}$ , the corresponding BTI lifetime under weak BTI stress was evaluated. It was found that assessing BTI lifetime via 1/f noise required only 35 s and 50 s for Si p- and n-MOSFETs, respectively. Furthermore, comparing the predicted lifetime derived from degradation data at various $T_{stress}$ with the actual BTI lifetimes (2550 s for p-MOSFETs and 2200 s for n-MOSFETs), the 1/f noise method emerged as the fastest and most accurate approach. This is attributed to its superior linearity and degradation amplitude over $T_{stress}$ on log-log scale. These findings contribute to proposing a novel method for obtaining the BTI lifetime of MOSFETs regarding the 1/f noise degradation, particularly for analog/mixed-signal (AMS) and radio frequency (RF) applications.