A DICE Flip-Flop Design by Resetting Redundancy Hardening for Single Event Upset Tolerance

IF 2.3 3区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE Transactions on Device and Materials Reliability Pub Date : 2025-03-14 DOI:10.1109/TDMR.2025.3570099

Yaohua Xu;Zeteng Liu;Yi Wang;Na Bai;Ye Liu

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引用次数: 0

Abstract

The standard cell library forms the foundation of chip design. Conducting rational and efficient radiation-hardening design and performance verification for the library is essential to ensure the safe on-orbit operation of aerospace components. This paper investigates the resettable dual interlocked storage cell (DICE) flip-flop (DICE-FF) from a radiation-hardened cell library and proposes a flip-flop (DICE-REFF) with reset-redundant control circuitry to improve its radiation tolerance. The study examines the effects of Single Event Upset (SEU) both before and after the redundancy hardening of the reset control, identifying sensitive layout regions and critical circuit nodes. Simulations show that the redundancy-hardened DICE-REFF demonstrates strong SEU tolerance, with a Linear Energy Transfer (LET) threshold of 37 MeV/mg/cm2. Additionally, the circuit area increased by only 5% compared to the non-hardened design, with no loss in performance. Additionally, a test chip was designed, and the SEU resistance of the flip-flop was validated through both fault injection and irradiation experiment. The study also explores the impact of different implementation strategies on fault rates.

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一种基于重置冗余强化的单事件干扰容限DICE触发器设计

标准单元库构成了芯片设计的基础。对库进行合理、高效的辐射强化设计和性能验证，是保障航天部件在轨安全运行的关键。研究了辐射硬化单元库中的可复位双互锁存储单元（DICE）触发器（DICE- ff），提出了一种带有复位冗余控制电路的触发器（DICE- reff），以提高其辐射容忍度。本研究考察了复位控制冗余强化前后单事件干扰（SEU）的影响，确定了敏感布局区域和关键电路节点。仿真结果表明，冗余强化的DICE-REFF具有较强的SEU容忍度，其线性能量转移（LET）阈值为37 MeV/mg/cm2。此外，与非硬化设计相比，电路面积仅增加了5%，而性能没有损失。设计了测试芯片，通过故障注入和辐照实验验证了触发器的SEU抗扰性。研究还探讨了不同的实施策略对故障率的影响。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Transactions on Device and Materials Reliability 工程技术-工程：电子与电气

CiteScore

4.80

自引率

5.00%

发文量

审稿时长

6-12 weeks

期刊介绍： The scope of the publication includes, but is not limited to Reliability of: Devices, Materials, Processes, Interfaces, Integrated Microsystems (including MEMS & Sensors), Transistors, Technology (CMOS, BiCMOS, etc.), Integrated Circuits (IC, SSI, MSI, LSI, ULSI, ELSI, etc.), Thin Film Transistor Applications. The measurement and understanding of the reliability of such entities at each phase, from the concept stage through research and development and into manufacturing scale-up, provides the overall database on the reliability of the devices, materials, processes, package and other necessities for the successful introduction of a product to market. This reliability database is the foundation for a quality product, which meets customer expectation. A product so developed has high reliability. High quality will be achieved because product weaknesses will have been found (root cause analysis) and designed out of the final product. This process of ever increasing reliability and quality will result in a superior product. In the end, reliability and quality are not one thing; but in a sense everything, which can be or has to be done to guarantee that the product successfully performs in the field under customer conditions. Our goal is to capture these advances. An additional objective is to focus cross fertilized communication in the state of the art of reliability of electronic materials and devices and provide fundamental understanding of basic phenomena that affect reliability. In addition, the publication is a forum for interdisciplinary studies on reliability. An overall goal is to provide leading edge/state of the art information, which is critically relevant to the creation of reliable products.