An Improved Steep-Slope Triple Metal Gate-Dual Dielectric-GaAs-Pocket-HTFET With Interface Trap Charges Analysis

Abstract

This article presents a Triple Metal Gate-Dual Dielectric-GaAs Pocket-Heterojunction Tunnel Field Effect Transistor (TMG-DD-GaAs-pocket-HTFET) for low-power and high-speed applications. To enhance carrier confinement and suppress ambipolar current, the device integrates triple gates (M1, M2, and M3) with a dual-dielectric stack of HfO2/SiO2 on a single layer. Additionally, SiGe is utilized as the source material to improve tunneling efficiency, while GaAs is employed as the pocket material to enhance carrier injection and overall device performance. The device’s characteristics are investigated using the Silvaco-TCAD simulator, focusing on its switching behavior and subthreshold performance. Further, the device’s immunity under interface trap charge (ITC) like positive (P-ITC), negative (N-ITC), and without interface trap charge (W-ITC) conditions is investigated. At a gate and drain voltage of 0.5 V, the W-ITC configuration achieves a low threshold voltage (Vth) of 0.19 V, an ultra-low subthreshold swing (SS) of 2.53 mV/decade, and a high ION of $5.83\times 10{^{\text {-5}}}$ A, with an exceptional ION/IOFF ratio of $1.42\times 10{^{{12}}}$ . The results show that the device’s performance is unaffected by the presence of positive or negative interface trap charges. These findings ensured that the proposed TMG-DD-GaAs-pocket-HTFET is a highly promising option for low-power, high-speed applications, with excellent scalability and enhanced performance. Key analog/RF parameters, including transconductance $(g_{m})$ , gate capacitance ( $C_{gd}$ , $C_{gs}$ ), cut-off frequency $(f_{T})$ , transconductance frequency product (TFP), and gain-bandwidth product (GBP), have been calculated. Additionally, an in-depth analysis under W-ITC condition is performed to assess the impact of varying gate work functions, gate lengths, and pocket materials on the device’s performance.