Vertical FET Optimization at Angstrom Nodes: A Comparative Study With Horizontal FET

IF 2.4 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE Journal of the Electron Devices Society Pub Date : 2025-08-14 DOI:10.1109/JEDS.2025.3599105

Junjong Lee;Jinsu Jeong;Seunghwan Lee;Sanguk Lee;Yonghwan Ahn;Minchan Kim;Gunryeol Cho;Sunmin Yeou;Rock-Hyun Baek

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引用次数: 0

Abstract

For the first time, this study presents two novel vertical FET (VFET) structures and conducts a quantitative analysis to assess the competitiveness of VFET in comparison to two types of horizontal FET (HFET) which are nanosheet FET (NSFET) and forksheet FET (FSFET) targeting Angstrom nodes. The conventional VFET (VFETCON) design exhibits a larger footprint than FSFET, delivering an inferior performance even when optimized for gate length. By contrast, the novel fork-shaped channel VFET (VFETFS) demonstrates a 10.5% reduction in the effective area compared to VFETCON, achieving a smaller footprint than FSFET with a large contact poly pitch (CPP). Additionally,

$\mathrm { VFET_{FS}}$

offers enhanced performance over

$\mathrm { VFET_{CON}}$

due to reduced capacitance. However,

$\mathrm { VFET_{FS}}$

shows more effective area and has a significantly lower drive current (Ion) than FSFET with a small CPP. Strategies to expand the silicide area effectively improve

$\mathrm { I_{on}}$

by reducing parasitic resistance, enabling NFET

$\mathrm { VFET_{FS}}$

to outperform FSFET. However, for PFET,

$\mathrm { VFET_{FS}}$

employing enlarged silicide areas exhibits lower performance compared with FSFET owing to the more substantial impact of performance degradation under non-stress conditions. The secondary device architecture,

$\mathrm { VFET_{FS}}$

with back-side contact (VFETBSC), further decreases the footprint, significantly lowers parasitic RC, and shows great heat dissipation when it has a large BSC area.

$\mathrm { VFET_{BSC}}$

requires a smaller effective area than FSFET with a 42 nm CPP, and its average performance for N/PFET surpasses that of FSFET.

查看原文本刊更多论文

埃节点垂直场效应管优化：与水平场效应管的比较研究

本研究首次提出了两种新型垂直场效应管（VFET）结构，并进行了定量分析，以评估VFET与两种针对埃节点的水平场效应管（HFET），即纳米片FET （NSFET）和叉片FET （ffet）的竞争力。传统的ffet （VFETCON）设计比ffet具有更大的占地面积，即使对栅极长度进行了优化，其性能也较差。相比之下，新型叉形通道VFET （VFETFS）的有效面积比VFETCON减少了10.5%，实现了比具有大接触聚节距（CPP）的ffet更小的占地面积。此外，$\ mathm {VFET_{FS}}$比$\ mathm {VFET_{CON}}$提供更强的性能，因为电容减少了。然而，$\mathrm {VFET_{FS}}$的有效面积更大，驱动电流（Ion）明显低于CPP较小的fset。扩大硅化面积的策略通过降低寄生电阻有效地改善了$\ mathm {I_{on}}$，使NFET $\ mathm {VFET_{FS}}$优于fset。然而，对于fet而言，由于在非应力条件下性能下降的影响更大，采用扩大硅化面积的$\ mathm {VFET_{FS}}$表现出比fset更低的性能。二次器件结构$\ mathm {VFET_{FS}}$ with backside contact （VFETBSC）进一步减小了占用空间，显著降低了寄生RC，当BSC面积较大时，散热效果良好。$\mathrm {VFET_{BSC}}$需要比fset更小的有效面积，42 nm CPP，其N/ ffet的平均性能超过fset。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Journal of the Electron Devices Society Biochemistry, Genetics and Molecular Biology-Biotechnology

CiteScore

5.20

自引率

4.30%

发文量

124

审稿时长

9 weeks

期刊介绍： The IEEE Journal of the Electron Devices Society (J-EDS) is an open-access, fully electronic scientific journal publishing papers ranging from fundamental to applied research that are scientifically rigorous and relevant to electron devices. The J-EDS publishes original and significant contributions relating to the theory, modelling, design, performance, and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanodevices, optoelectronics, photovoltaics, power IC''s, and micro-sensors. Tutorial and review papers on these subjects are, also, published. And, occasionally special issues with a collection of papers on particular areas in more depth and breadth are, also, published. J-EDS publishes all papers that are judged to be technically valid and original.