Complementary Vertical FETs (CVFETs) Enabled by a Novel Dual-Side Process

IF 4.5 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC
Y. Du;Y. K. Zhang;H. L. Zhu;B. H. Wang;Q. Wang;W. L. Liu;Z. C. Wang;T. R. Luo;S. S. Lu;P. H. Sun;X. Y. Chen;Y. T. Zheng;H. Yang;J. J. Li;J. F. Li;X. L. Wang;J. Luo;W. W. Wang;B. W. Dai;T. C. Ye
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引用次数: 0

Abstract

We demonstrated the monolithically integrated complementary vertical-channel field-effect-transistor (CVFET) inverters with an innovative dual-side process (DSP). Good electrical characteristics for both NMOS and PMOS were achieved: transconductance of $69~\mu $ S/ $\mu $ m, ${\mathrm{I}}_{\text {on}} = 18~\mu $ A/ $\mu $ m (@ VGS – ${\mathrm{V}}_{\text {T}} =0.45$ V, ${\mathrm{V}}_{\text {DD}}=0.65$ V), Ion/ ${\mathrm{I}}_{\text {off}} = 3.1\times 10^{{6}}$ , SS =69 mV/dec and DIBL =12 mV/V for the top NMOS, and transconductance of $592~\mu $ S/ $\mu $ m, ${\mathrm{I}}_{\text {on}} = 136~\mu $ A/ $\mu $ m (@ VGS – ${\mathrm{V}}_{\text {T}} = -0.45$ V, ${\mathrm{V}}_{\text {DD}}= -0.65$ V), Ion/ ${\mathrm{I}}_{\text {off}} = 5.4\times 10^{{6}}$ , SS =72 mV/dec and DIBL=18 mV/V for the bottom PMOS. The functional CVFET inverters show well-balanced voltage transfer characteristics (VTC) up to 1.2 V with a maximum gain of 13 V/V. Furthermore, the CVFETs also featured with crystal-Si vertical channels and common self-aligned high- $\kappa $ metal gates. The CVFET structure and its integration scheme are strong candidates for the applications of advanced logic technologies.
新型双面工艺实现互补垂直场效应管(cvfet)
我们展示了具有创新双侧工艺(DSP)的单片集成互补垂直沟道场效应晶体管(CVFET)逆变器。NMOS和PMOS均获得了良好的电气特性:$69~\mu $ S/ $\mu $ m、${\mathrm{I}}_{\text {on}} = 18~\mu $ A/ $\mu $ m (@ VGS - ${\mathrm{V}}_{\text {T}} =0.45$ V、${\mathrm{V}}_{\text {DD}}=0.65$ V)、Ion/ ${\mathrm{I}}_{\text {off}} = 3.1\times 10^{{6}}$、SS =69 mV/dec、DIBL= 12 mV/V)、$592~\mu $ S/ $\mu $ m、${\mathrm{I}}_{\text {on}} = 136~\mu $ A/ $\mu $ m (@ VGS - ${\mathrm{V}}_{\text {T}} = -0.45$ V、${\mathrm{V}}_{\text {DD}}= -0.65$ V)、Ion/ ${\mathrm{I}}_{\text {off}} = 5.4\times 10^{{6}}$、SS =72 mV/dec、DIBL=18 mV/V)的跨导率为底部PMOS。该功能CVFET逆变器具有良好的平衡电压转移特性(VTC),最高可达1.2 V,最大增益为13 V/V。此外,cvfet还具有晶体硅垂直沟道和常见的自对准高$\kappa $金属栅极。CVFET结构及其集成方案是先进逻辑技术应用的有力候选者。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
IEEE Electron Device Letters
IEEE Electron Device Letters 工程技术-工程:电子与电气
CiteScore
8.20
自引率
10.20%
发文量
551
审稿时长
1.4 months
期刊介绍: IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanoelectronics, optoelectronics, photovoltaics, power ICs and micro-sensors.
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