Impact of Gate Misalignment on Analog Performance Metrics of Nanoscale Independent Dual-Gate IGZO FETs for BEOL-Memory Sense Amplifier Design

IF 4.5 2区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE Electron Device Letters Pub Date : 2025-06-30 DOI:10.1109/LED.2025.3584150

Xiaoyi Zhang;Kaifei Chen;Xufan Li;Yue Zhao;Kexin Shang;Guanhua Yang;Lingfei Wang;Ling Li

{"title":"Impact of Gate Misalignment on Analog Performance Metrics of Nanoscale Independent Dual-Gate IGZO FETs for BEOL-Memory Sense Amplifier Design","authors":"Xiaoyi Zhang;Kaifei Chen;Xufan Li;Yue Zhao;Kexin Shang;Guanhua Yang;Lingfei Wang;Ling Li","doi":"10.1109/LED.2025.3584150","DOIUrl":null,"url":null,"abstract":"For high-density 3D DRAM, the voltage drops of Through-Silicon-Via are nonnegligible among stacks of layers, requiring high-gain sense amplifier (SA) design. Considering back-end of line (BEOL) compatibility, independent dual-gate (IDG) IGZO FETs are promising not only for multi-bit DRAM design but also for applications in SA input transistors. This letter investigates the important analog figures of merit (FOMs) of DG IGZO FETs under various operating conditions. TCAD simulations validated by experimental data reveal that top-gate misalignment (ranging from 25% to 100%) exhibits electric field distribution variations. The trade-off between transconductance generation factor and intrinsic gain is obviously observed. Such a top-gate misalignment effect causes threshold voltage shifts and circuit mismatches in DRAM SAs, and the mismatch can be compensated by independent top-gate biasing, enabling threshold voltage modulation. IDG IGZO FETs indicate superior gain performance compared to single-gate IGZO FETs and lower leakage current than Si-based FETs, which are critical for SA input transistors. These findings provide important guidance for optimizing dual-gate IGZO FETs in analog applications, particularly for BEOL-memory SAs that need both high gain and fast response speed.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 9","pages":"1652-1655"},"PeriodicalIF":4.5000,"publicationDate":"2025-06-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Electron Device Letters","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/11058973/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}

引用次数: 0

Abstract

For high-density 3D DRAM, the voltage drops of Through-Silicon-Via are nonnegligible among stacks of layers, requiring high-gain sense amplifier (SA) design. Considering back-end of line (BEOL) compatibility, independent dual-gate (IDG) IGZO FETs are promising not only for multi-bit DRAM design but also for applications in SA input transistors. This letter investigates the important analog figures of merit (FOMs) of DG IGZO FETs under various operating conditions. TCAD simulations validated by experimental data reveal that top-gate misalignment (ranging from 25% to 100%) exhibits electric field distribution variations. The trade-off between transconductance generation factor and intrinsic gain is obviously observed. Such a top-gate misalignment effect causes threshold voltage shifts and circuit mismatches in DRAM SAs, and the mismatch can be compensated by independent top-gate biasing, enabling threshold voltage modulation. IDG IGZO FETs indicate superior gain performance compared to single-gate IGZO FETs and lower leakage current than Si-based FETs, which are critical for SA input transistors. These findings provide important guidance for optimizing dual-gate IGZO FETs in analog applications, particularly for BEOL-memory SAs that need both high gain and fast response speed.

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栅极失调对用于beol -记忆感测放大器设计的纳米级独立双栅IGZO fet模拟性能指标的影响

对于高密度3D DRAM，通硅通孔的电压降在层间的堆叠是不可忽略的，需要高增益感测放大器（SA）的设计。考虑到线后端（BEOL）兼容性，独立双栅（IDG） IGZO场效应管不仅适用于多位DRAM设计，也适用于SA输入晶体管。本文研究了不同工作条件下DG IGZO fet的重要模拟功值。实验数据验证了TCAD模拟结果，结果表明顶栅不对准（范围从25%到100%）表现出电场分布的变化。跨导产生因子与固有增益之间的权衡是显而易见的。这种顶门失调效应会导致DRAM SAs中的阈值电压偏移和电路不匹配，而这种不匹配可以通过独立的顶门偏置来补偿，从而实现阈值电压调制。与单栅极IGZO fet相比，IDG IGZO fet具有更好的增益性能，并且比si基fet具有更低的漏电流，这对于SA输入晶体管至关重要。这些发现为优化模拟应用中的双栅IGZO fet提供了重要指导，特别是对于需要高增益和快速响应速度的beol存储器sa。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Electron Device Letters 工程技术-工程：电子与电气

CiteScore

8.20

自引率

10.20%

发文量

551

审稿时长

1.4 months

期刊介绍： IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanoelectronics, optoelectronics, photovoltaics, power ICs and micro-sensors.