Fabrication of p-SiGe/n-Si NSs CFET Using Single-Step Ge-Selective Etching Method and Wafer-Bonding Technique

Abstract

The fabrication of heterogeneous p-SiGe/n-Si channel CFETs presents significant challenges. In a single fin structure, selectively etching the Si layer while preserving the SiGe layer for the p-FET and selectively etching the SiGe layer while preserving the Si layer for the n-FET requires two opposite etching steps. This process becomes particularly complex because of the additional local lithography required. In this study, CFETs with multiply stacked p-SiGe/n-Si nanosheet channels by using Ge interlayers as sacrificial layers are demonstrated based on the wafer-bonding process flow.