{"title":"1200 V Fully-Vertical GaN-on-Si Power MOSFETs","authors":"Yuchuan Ma;Hang Chen;Shuhui Zhang;Huantao Duan;Bin Hu;Huimei Ma;Jianfei Shen;Minghua Zhu;Jin Rao;Chao Liu","doi":"10.1109/LED.2025.3586947","DOIUrl":null,"url":null,"abstract":"We report 1200 V fully-vertical GaN-on-Si trench MOSFETs with fluorine implanted termination (FIT-MOS). The FIT region with negative fixed charges becomes resistive and naturally isolates the discrete devices, replacing the conventional mesa etching termination (MET), eliminating the electric field crowding effect at the mesa edges, therefore boosting the breakdown voltage of the FIT-MOS to 1277 V from 567 V of the MET-MOS. Moreover, the as-fabricated FIT-MOS exhibits a threshold voltage (<inline-formula> <tex-math>${V}_{\\textit {TH}}\\text {)}$ </tex-math></inline-formula> of 3.3 V, an ON/OFF ratio of <inline-formula> <tex-math>$\\sim 10^{{7}}$ </tex-math></inline-formula>, together with a specific ON-resistance (<inline-formula> <tex-math>${R}_{\\textit {ON}, \\textit {SP}}\\text {)}$ </tex-math></inline-formula> of 5.6 m<inline-formula> <tex-math>$\\Omega \\cdot $ </tex-math></inline-formula>cm2. These results show great potential of cost-effective GaN-on-Si vertical transistors for kV-class applications.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 9","pages":"1513-1516"},"PeriodicalIF":4.5000,"publicationDate":"2025-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Electron Device Letters","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/11072711/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
We report 1200 V fully-vertical GaN-on-Si trench MOSFETs with fluorine implanted termination (FIT-MOS). The FIT region with negative fixed charges becomes resistive and naturally isolates the discrete devices, replacing the conventional mesa etching termination (MET), eliminating the electric field crowding effect at the mesa edges, therefore boosting the breakdown voltage of the FIT-MOS to 1277 V from 567 V of the MET-MOS. Moreover, the as-fabricated FIT-MOS exhibits a threshold voltage (${V}_{\textit {TH}}\text {)}$ of 3.3 V, an ON/OFF ratio of $\sim 10^{{7}}$ , together with a specific ON-resistance (${R}_{\textit {ON}, \textit {SP}}\text {)}$ of 5.6 m$\Omega \cdot $ cm2. These results show great potential of cost-effective GaN-on-Si vertical transistors for kV-class applications.
期刊介绍:
IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanoelectronics, optoelectronics, photovoltaics, power ICs and micro-sensors.