{"title":"Monolithic Integrated, Reconfigurable Gallium Oxide NAND/NOR Gates With Ferroelectric AlScN Gate Stack","authors":"Sisung Yoon;Seungyoon Oh;Yoojin Lim;Ji-Hyeon Park;Dae-Woo Jeon;Geonwook Yoo","doi":"10.1109/LED.2025.3584764","DOIUrl":null,"url":null,"abstract":"We present monolithic integrated, <inline-formula> <tex-math>$\\alpha $ </tex-math></inline-formula>-Ga2O3 reconfigurable NAND and NOR logic gates. Fabricated <inline-formula> <tex-math>$\\alpha $ </tex-math></inline-formula>-Ga2O3 field-effect transistors with a ferroelectric AlScN gate stack (FeFET) exhibit memory window of up to 5.5 V at <inline-formula> <tex-math>${V}_{\\text {DS}} = 1$ </tex-math></inline-formula> V. Threshold voltage modulation of ~3.8 V is achieved via a program (10 V, 1 s) and erase pulse (−20 V, 1 s), respectively. Moreover, voltage transfer curves of the logic circuit as an inverter confirm hysteretic behaviors with a higher gain during a reverse sweep. Finally, reconfigurable logic operations are successfully demonstrated via two distinct input pulses and a source bias to the driver FeFET. The results demonstrate viability of monolithic integrated, compact Ga2O3 logic circuits.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 9","pages":"1501-1504"},"PeriodicalIF":4.5000,"publicationDate":"2025-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Electron Device Letters","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/11062685/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
We present monolithic integrated, $\alpha $ -Ga2O3 reconfigurable NAND and NOR logic gates. Fabricated $\alpha $ -Ga2O3 field-effect transistors with a ferroelectric AlScN gate stack (FeFET) exhibit memory window of up to 5.5 V at ${V}_{\text {DS}} = 1$ V. Threshold voltage modulation of ~3.8 V is achieved via a program (10 V, 1 s) and erase pulse (−20 V, 1 s), respectively. Moreover, voltage transfer curves of the logic circuit as an inverter confirm hysteretic behaviors with a higher gain during a reverse sweep. Finally, reconfigurable logic operations are successfully demonstrated via two distinct input pulses and a source bias to the driver FeFET. The results demonstrate viability of monolithic integrated, compact Ga2O3 logic circuits.
期刊介绍:
IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanoelectronics, optoelectronics, photovoltaics, power ICs and micro-sensors.