{"title":"Total Ionizing Dose Hardening Methodology in Back Gate Embedded SOI MOSFETs With Ultrathin Buried Oxide","authors":"Yuxin Liu;Qiang Liu;Jin Chen;Wenjie Yu","doi":"10.1109/LED.2025.3587666","DOIUrl":null,"url":null,"abstract":"A novel total ionizing dose (TID) hardening method is proposed based on the innovative back gate embedded silicon on insulator (BGESOI) technology. By elaborately designing the manufacturing process, the symmetric split gate configuration is constructed within the standard CMOS platforms. Notably, the BGESOI MOSFET features ~6nm buried oxide, which is thinner than that in typical fully depleted silicon on insulator (FDSOI) devices, thereby achieving enhanced TID tolerance. The device exhibits a threshold voltage (<inline-formula> <tex-math>${V}_{\\text {th}}\\text {)}$ </tex-math></inline-formula> shift of around -30mV @7Mrad(Si) which can be further compensated by adjusting the back gate bias by only ~80mV thanks to its ultrahigh body factor (<inline-formula> <tex-math>$\\ge 350$ </tex-math></inline-formula>mV/V). This work presents a promising solution for robust TID hardening in extremely harsh radiation environments.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 9","pages":"1465-1468"},"PeriodicalIF":4.5000,"publicationDate":"2025-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Electron Device Letters","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/11077443/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
A novel total ionizing dose (TID) hardening method is proposed based on the innovative back gate embedded silicon on insulator (BGESOI) technology. By elaborately designing the manufacturing process, the symmetric split gate configuration is constructed within the standard CMOS platforms. Notably, the BGESOI MOSFET features ~6nm buried oxide, which is thinner than that in typical fully depleted silicon on insulator (FDSOI) devices, thereby achieving enhanced TID tolerance. The device exhibits a threshold voltage (${V}_{\text {th}}\text {)}$ shift of around -30mV @7Mrad(Si) which can be further compensated by adjusting the back gate bias by only ~80mV thanks to its ultrahigh body factor ($\ge 350$ mV/V). This work presents a promising solution for robust TID hardening in extremely harsh radiation environments.
期刊介绍:
IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanoelectronics, optoelectronics, photovoltaics, power ICs and micro-sensors.