Design Optimizations of Micrometer SiC CMOS Devices for High-Temperature IC Applications

Abstract

This article proposes the generalized design guideline for micrometer silicon carbide (SiC) complementary metal-oxide-semiconductor (CMOS) devices for integrated circuit (IC) applications. The design window of 1- $\mu $ m SiC CMOS devices, which considers device operation voltage, on-state current, short channel effect (SCE), and subthreshold swing (SS), is proposed to show the design margins of the gate oxide thickness and channel doping concentration. The performance of CMOS devices in 1- $\mu $ m SiC CMOS processes is used to demonstrate the effectiveness of the proposed design window. SiC-based buffer chain circuits are tested to demonstrate circuit operating speed and power consumption. The devices and circuits are fully characterized from 25 ° C to 300 ° C. It has been demonstrated that further design improvements for SiC CMOS devices are needed before large-scale implementation due to their strong SCE, high SS, and lowon-state current. On the other hand, SiC ICs show less degradation with increasing temperatures compared to Si ICs, making them promising for high-temperature applications.