Backside Contact Misalignment-Induced TDDB in BSPDN CFET

Abstract

Complementary field-effect transistors (CFETs) and backside contacts (BSCs) are the effective approaches for reducing cell layout size. However, since BSC is formed post wafer bonding and extreme wafer thinning, bonding-induced wafer distortion inevitably introduces BSC alignment challenges, with control of its misalignment toward the layers on the wafer’s frontside requiring careful attention. As misalignment increases, the distance between the BSC and the gate decreases, resulting in a strong electric field concentration in the bottom oxide of the CFET. In this study, metal–insulator–metal (MIM) capacitors with gate-to-BSC overlap caused by misalignment were fabricated and used to calibrate a time-dependent dielectric breakdown (TDDB) simulation. Additionally, using 3-D technology computer-aided design (TCAD), we extracted the electric field applied to the bottom oxide as a function of misalignment, based on both experimental data and the calibrated CFET model. By inputting the extracted electric field into the TDDB simulator, we evaluated the degradation of oxide lifetime. The results show that using Mo metal for the BSC significantly reduces the electric field compared to W metal, thereby leading to an overall increase in TDDB lifetime. These findings provide valuable insights into the impact of BSC misalignment on CFET reliability and highlight the importance of material selection and precise alignment control for process optimization.