{"title":"Amalgamated organic polymer of PVA/P(VDF-TrFE) as back gate dielectric in WS2 FET fabrication","authors":"Arpita Roy, Biplob Mondal","doi":"10.1016/j.mssp.2025.109979","DOIUrl":null,"url":null,"abstract":"<div><div>2D WS<sub>2</sub> channel combined with organic polymer dielectrics have garnered significant attention due to their promising applications in FETs, owing to their exceptional mechanical flexibility and cost-effective fabrication process. WS<sub>2</sub> FETs with polymer dielectrics not only surpass the thermal constraints but also enable low-voltage operation, providing a notable advantage over traditional devices. Conventional SiO<sub>2</sub> dielectrics often suffer from high oxide trap density, which adversely affects device performance. To address these issues, this study proposes the incorporation of a stack of low-k and high-k organic polymer dielectrics in WS<sub>2</sub>-FET fabrication, enabling low-voltage operation at room temperature. Polymer gate dielectrics have demonstrated a remarkable ability to enhance the efficiency of 2D WS<sub>2</sub>-FETs, contributing to the development of versatile and energy-efficient device architectures. This work demonstrates the fabrication and electrical characterization of WS<sub>2</sub>-FETs using a PVA/P(VDF-TrFE) organic polymer dielectric stack. The findings reveal that the few-layer WS<sub>2</sub>-FET structures exhibit a field-effect mobility (μ<sub>FE</sub>) of ∼215.2 cm<sup>2</sup>/Vs and I<sub>ON</sub>/I<sub>OFF</sub> current ratio of around ∼10<sup>7</sup>.</div></div>","PeriodicalId":18240,"journal":{"name":"Materials Science in Semiconductor Processing","volume":"200 ","pages":"Article 109979"},"PeriodicalIF":4.6000,"publicationDate":"2025-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Materials Science in Semiconductor Processing","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S1369800125007164","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
2D WS2 channel combined with organic polymer dielectrics have garnered significant attention due to their promising applications in FETs, owing to their exceptional mechanical flexibility and cost-effective fabrication process. WS2 FETs with polymer dielectrics not only surpass the thermal constraints but also enable low-voltage operation, providing a notable advantage over traditional devices. Conventional SiO2 dielectrics often suffer from high oxide trap density, which adversely affects device performance. To address these issues, this study proposes the incorporation of a stack of low-k and high-k organic polymer dielectrics in WS2-FET fabrication, enabling low-voltage operation at room temperature. Polymer gate dielectrics have demonstrated a remarkable ability to enhance the efficiency of 2D WS2-FETs, contributing to the development of versatile and energy-efficient device architectures. This work demonstrates the fabrication and electrical characterization of WS2-FETs using a PVA/P(VDF-TrFE) organic polymer dielectric stack. The findings reveal that the few-layer WS2-FET structures exhibit a field-effect mobility (μFE) of ∼215.2 cm2/Vs and ION/IOFF current ratio of around ∼107.
期刊介绍:
Materials Science in Semiconductor Processing provides a unique forum for the discussion of novel processing, applications and theoretical studies of functional materials and devices for (opto)electronics, sensors, detectors, biotechnology and green energy.
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