Enhancing Current Gain in Polysilicon Emitter Bipolar Transistors Through Emitter-Base Interface Engineering

Abstract

Polysilicon is extensively employed as a material for emitters in vertical bipolar junction transistors (BJTs) to achieve high current gain (beta). To enhance the electrical properties of polysilicon emitter BJTs, meticulous engineering of the interface between the emitter polysilicon and the base is crucial. This paper begins by elucidating the sources and implications of variations in interface oxide thickness observed in polysilicon emitter PNP transistors. The deposition of the polysilicon emitter is performed using the low-pressure chemical vapor deposition (LPCVD) furnace process. The formation of native oxide during the LPCVD furnace loading results in significant discrepancies in current gain across different positions within the furnace boat. To understand the underlying mechanisms, we employ thickness measurements through ellipsometry, transmission electron microscopy (TEM) grain analysis, and electrical characterization. To mitigate these variations, several experimental approaches have been pursued. This paper reports that the application of a thin layer of chemical oxide at the interface—achieved through an HF-first RCA clean prior to polysilicon deposition—can establish a controllable, repeatable, and uniform layer of interface oxide. This consistent chemical oxide effectively passivates the silicon surface, leading to stable and uniform electrical performance across all furnace boat positions, thus eliminating variations attributed to furnace loading and waiting times. The proposed solution significantly improves furnace utilization, yield, process capability indices (Cp and Cpk), while also reducing associated costs. Furthermore, this paper introduces an innovative method to modify the emitter-base interface utilizing plasma surface treatment, aimed at enhancing the average current gain performance across all boat positions without compromising breakdown and leakage characteristics. The plasma treatment, which incorporates the application of bias power, induces surface roughness that inhibits the epitaxial realignment of the emitter polysilicon, thereby improving current gain.