Sputtering impact on warpage in FOWLP

Abstract

Fan-out wafer level packaging (FOWLP), an advanced packaging technology that can achieve high performance and miniaturisation, has become a subject of considerable research interest. As one of the important high-temperature steps in the FOWLP process, the influence of the sputtering step on the amount of wafer deformation is a key element in the study of the reliability of FOWLP. This study investigates the changes in warpage during the sputtering steps through both simulation and experimental approaches. Particularly, for the degassing chamber (Degas) that has the greatest impact on wafer warpage, the study analyzed its working principle and the mechanism of warpage formation. It is proposed that the primary causes of the warpage change in the Degas chamber are the maximum wafer temperature and the maximum temperature difference. Based on this, simulation and experimental studies were conducted on wafer temperature and warpage changes under different heat flow rate, while also considering silicon chip thickness ratio, to provide insights into more methods for mitigating wafer warpage in PVD (Physical Vapor Deposition) processes. The results of the study show that the wafer temperature is positively correlated with the heat flow rate and high wafer temperature can lead to wafer warpage greater than 5 mm, which is a great challenge to the process. In addition, the article uses simulation to verify the impact of wafer silicon chip thickness ratio on warpage, verifying the conclusion that the wafer warpage is the largest when the silicon chip thickness ratio is around 20 %–30 %.