A Compact 8-to-16 GHz GaN Nonuniform Distributed PA With Double Feeding Line Matching Structure Presenting 43.2% Average PAE

IF 2 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Zhaowu Wang;Dexin Shi;Xinyan Li;Shu Ma;Ronglin Chen;Ze Yu;Ziao Wang;Shijie Chen;Xiaochen Tang;Yong Wang
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引用次数: 0

Abstract

This letter focuses on improving power added efficiency (PAE) of high-power nonuniform distributed power amplifier (NDPA). A double feeding line matching (DFLM) structure is proposed, where a double-T-type and a $\pi $ -type DFLM networks are inserted into drain transmission-line (TL) and gate TL of classical designs, respectively. These optimize load/source impedance for each transistor, improving the output power and PAE. The NPDA monolithic microwave integrated circuit (MMIC) is fabricated with a commercial 0.25- $\mu $ m gallium nitride (GaN) process. The measurement results show that the proposed NDPA achieves output power of 37.6-to-40.2 dBm, and PAE of 37.6%-to-50.3% at 8-to-16 GHz, with the chip area of merely 3.5 mm2. The proposed NPDA outperforms the state-of-the-art broadband power amplifier (PA) in PAE with a much smaller chip area.
一种具有双馈线匹配结构的8 ~ 16 GHz GaN非均匀分布PA,平均PAE为43.2%
本文的重点是提高大功率非均匀分布式功率放大器(NDPA)的功率附加效率(PAE)。提出了一种双馈线匹配(DFLM)结构,将双t型和$\pi $型DFLM网络分别插入经典设计的漏极输导在线(TL)和栅极输导在线(TL)中。这些优化负载/源阻抗为每个晶体管,提高输出功率和PAE。NPDA单片微波集成电路(MMIC)采用商用0.25- $\mu $ m氮化镓(GaN)工艺制备。测量结果表明,该NDPA的输出功率为37.6 ~ 40.2 dBm, PAE为37.6%-to-50.3% at 8-to-16 GHz, with the chip area of merely 3.5 mm2. The proposed NPDA outperforms the state-of-the-art broadband power amplifier (PA) in PAE with a much smaller chip area.
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
IEEE Solid-State Circuits Letters
IEEE Solid-State Circuits Letters Engineering-Electrical and Electronic Engineering
CiteScore
4.30
自引率
3.70%
发文量
52
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