Ternary CMOS Compact Model for Low Power On-Chip Memory Applications

Abstract

In this work, we present a tunneling based ternary CMOS (T-CMOS) compact model for low power ternary-SRAM (T-SRAM) design using CMOS technology. By designing compact model parameters of band-to-band tunneling current $(I_{\mathrm { BTBT}})$ according to effective doping concentration of T-CMOS, more accurate current model has been obtained in comparison with the conventional $I_{\mathrm { BTBT}}$ models. In addition, parasitic capacitance models are obtained for transient operation. Comparing model and experimental data, it enables the prediction of T-CMOS performance under various $V_{\mathrm { DD}}$ conditions. The model is validated to be more suitable for T-CMOS with low power on-chip memory applications.